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authorblueswir1 <blueswir1@c046a42c-6fe2-441c-8c8c-71466251a162>2009-03-07 20:50:01 +0000
committerblueswir1 <blueswir1@c046a42c-6fe2-441c-8c8c-71466251a162>2009-03-07 20:50:01 +0000
commitf6b868fc5899899774eecc43fc21b3a6c6ecfa9a (patch)
tree00cf84e46ee8213d417d41e5cc61506d7d5f4ff8 /target-ppc/op_helper.c
parentc5e97233e8c8e53aab1b80b5e9891a71c4edea3e (diff)
downloadqemu-f6b868fc5899899774eecc43fc21b3a6c6ecfa9a.tar.gz
Implement slbmte
In order to modify SLB entries on recent PPC64 machines, the slbmte instruction is used. This patch implements the slbmte instruction and makes the "bridge" mode code use the slb set functions, so we can move the SLB into the CPU struct later. This is required for Linux to run on PPC64. Signed-off-by: Alexander Graf <alex@csgraf.de> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6747 c046a42c-6fe2-441c-8c8c-71466251a162
Diffstat (limited to 'target-ppc/op_helper.c')
-rw-r--r--target-ppc/op_helper.c8
1 files changed, 6 insertions, 2 deletions
diff --git a/target-ppc/op_helper.c b/target-ppc/op_helper.c
index 3afd217bc2..76fe8f6f8c 100644
--- a/target-ppc/op_helper.c
+++ b/target-ppc/op_helper.c
@@ -3752,6 +3752,10 @@ void tlb_fill (target_ulong addr, int is_write, int mmu_idx, void *retaddr)
/* Segment registers load and store */
target_ulong helper_load_sr (target_ulong sr_num)
{
+#if defined(TARGET_PPC64)
+ if (env->mmu_model & POWERPC_MMU_64)
+ return ppc_load_sr(env, sr_num);
+#endif
return env->sr[sr_num];
}
@@ -3767,9 +3771,9 @@ target_ulong helper_load_slb (target_ulong slb_nr)
return ppc_load_slb(env, slb_nr);
}
-void helper_store_slb (target_ulong slb_nr, target_ulong rs)
+void helper_store_slb (target_ulong rb, target_ulong rs)
{
- ppc_store_slb(env, slb_nr, rs);
+ ppc_store_slb(env, rb, rs);
}
void helper_slbia (void)