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| author | Tom Musta <tommusta@gmail.com> | 2013-10-22 22:06:17 +1100 |
|---|---|---|
| committer | Alexander Graf <agraf@suse.de> | 2013-12-20 01:57:47 +0100 |
| commit | 1f29871cb7518692cf5c1fa8c19b117c789ff7f0 (patch) | |
| tree | 7c8650829b497d5ebac5bd6a21ed3d09b8c81f19 /target-ppc/translate.c | |
| parent | 74f239975501cf0ad886a5d40ce40aecbb9dc0b2 (diff) | |
| download | qemu-1f29871cb7518692cf5c1fa8c19b117c789ff7f0.tar.gz | |
Add MSR VSX and Associated Exception
This patch adds support for the VSX bit of the PowerPC Machine
State Register (MSR) as well as the corresponding VSX Unavailable
exception.
The VSX bit is added to the defined bits masks of the Power7 and
Power8 CPU models.
Signed-off-by: Tom Musta <tommusta@gmail.com>
Signed-off-by: Anton Blanchard <anton@samba.org>
Signed-off-by: Alexander Graf <agraf@suse.de>
Diffstat (limited to 'target-ppc/translate.c')
| -rw-r--r-- | target-ppc/translate.c | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/target-ppc/translate.c b/target-ppc/translate.c index 66c777174c..415f5d14e1 100644 --- a/target-ppc/translate.c +++ b/target-ppc/translate.c @@ -195,6 +195,7 @@ typedef struct DisasContext { #endif int fpu_enabled; int altivec_enabled; + int vsx_enabled; int spe_enabled; ppc_spr_t *spr_cb; /* Needed to check rights for mfspr/mtspr */ int singlestep_enabled; @@ -9759,6 +9760,11 @@ static inline void gen_intermediate_code_internal(PowerPCCPU *cpu, ctx.altivec_enabled = msr_vr; else ctx.altivec_enabled = 0; + if ((env->flags & POWERPC_FLAG_VSX) && msr_vsx) { + ctx.vsx_enabled = msr_vsx; + } else { + ctx.vsx_enabled = 0; + } if ((env->flags & POWERPC_FLAG_SE) && msr_se) ctx.singlestep_enabled = CPU_SINGLE_STEP; else |