diff options
| author | Tom Musta <tommusta@gmail.com> | 2014-02-12 15:23:01 -0600 |
|---|---|---|
| committer | Alexander Graf <agraf@suse.de> | 2014-03-05 03:06:54 +0100 |
| commit | 63be09365a9a4658060e85ce013cc0beaeac25e5 (patch) | |
| tree | b9eca6491e45a44bdd1d0e78c78c022c358e819c /target-ppc/translate.c | |
| parent | aa9e930c8870d06a20b356785d3ec7d9a942a29f (diff) | |
| download | qemu-63be09365a9a4658060e85ce013cc0beaeac25e5.tar.gz | |
target-ppc: Altivec 2.07: Multiply Even/Odd Word Instructions
This patch adds the Multilpy Even/Odd Word instructions that are introduced
in Power ISA Version 2.07:
- Vector Multiply Even Unsigned Word (vmuleuw)
- Vector Multiply Even Signed Word (vmulesw)
- Vector Multiply Odd Unsigned Word (vmulouw)
- Vector Multiply Odd Signed Word (vmulosw)
Signed-off-by: Tom Musta <tommusta@gmail.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
Diffstat (limited to 'target-ppc/translate.c')
| -rw-r--r-- | target-ppc/translate.c | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/target-ppc/translate.c b/target-ppc/translate.c index b1986f4b07..4d2579df86 100644 --- a/target-ppc/translate.c +++ b/target-ppc/translate.c @@ -6963,12 +6963,16 @@ GEN_VXFORM(vmrglh, 6, 5); GEN_VXFORM(vmrglw, 6, 6); GEN_VXFORM(vmuloub, 4, 0); GEN_VXFORM(vmulouh, 4, 1); +GEN_VXFORM(vmulouw, 4, 2); GEN_VXFORM(vmulosb, 4, 4); GEN_VXFORM(vmulosh, 4, 5); +GEN_VXFORM(vmulosw, 4, 6); GEN_VXFORM(vmuleub, 4, 8); GEN_VXFORM(vmuleuh, 4, 9); +GEN_VXFORM(vmuleuw, 4, 10); GEN_VXFORM(vmulesb, 4, 12); GEN_VXFORM(vmulesh, 4, 13); +GEN_VXFORM(vmulesw, 4, 14); GEN_VXFORM(vslb, 2, 4); GEN_VXFORM(vslh, 2, 5); GEN_VXFORM(vslw, 2, 6); @@ -10371,12 +10375,16 @@ GEN_VXFORM(vmrglh, 6, 5), GEN_VXFORM(vmrglw, 6, 6), GEN_VXFORM(vmuloub, 4, 0), GEN_VXFORM(vmulouh, 4, 1), +GEN_VXFORM_207(vmulouw, 4, 2), GEN_VXFORM(vmulosb, 4, 4), GEN_VXFORM(vmulosh, 4, 5), +GEN_VXFORM_207(vmulosw, 4, 6), GEN_VXFORM(vmuleub, 4, 8), GEN_VXFORM(vmuleuh, 4, 9), +GEN_VXFORM_207(vmuleuw, 4, 10), GEN_VXFORM(vmulesb, 4, 12), GEN_VXFORM(vmulesh, 4, 13), +GEN_VXFORM_207(vmulesw, 4, 14), GEN_VXFORM(vslb, 2, 4), GEN_VXFORM(vslh, 2, 5), GEN_VXFORM(vslw, 2, 6), |