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authorTom Musta <tommusta@gmail.com>2014-01-07 10:06:10 -0600
committerAlexander Graf <agraf@suse.de>2014-03-05 03:06:44 +0100
commit66c3e32841f185243efa59381ab7721b24deca35 (patch)
tree046a51c314aaa65e3e655548335e3a7d32653143 /target-ppc/translate.c
parentce8ca30b398fb74e522be1a9ea87aa7868f27428 (diff)
downloadqemu-66c3e32841f185243efa59381ab7721b24deca35.tar.gz
target-ppc: Add ISA2.06 lfiwzx Instruction
This patch adds the Load Floating Point as Integer Word and Zero Indexed (lfiwzx) instruction which was introduced in Power ISA 2.06. Signed-off-by: Tom Musta <tommusta@gmail.com> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Alexander Graf <agraf@suse.de>
Diffstat (limited to 'target-ppc/translate.c')
-rw-r--r--target-ppc/translate.c15
1 files changed, 15 insertions, 0 deletions
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index c9aebc5e84..951f15e055 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -3508,6 +3508,20 @@ static void gen_lfiwax(DisasContext *ctx)
tcg_temp_free(t0);
}
+/* lfiwzx */
+static void gen_lfiwzx(DisasContext *ctx)
+{
+ TCGv EA;
+ if (unlikely(!ctx->fpu_enabled)) {
+ gen_exception(ctx, POWERPC_EXCP_FPU);
+ return;
+ }
+ gen_set_access_type(ctx, ACCESS_FLOAT);
+ EA = tcg_temp_new();
+ gen_addr_reg_index(ctx, EA);
+ gen_qemu_ld32u_i64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
+ tcg_temp_free(EA);
+}
/*** Floating-point store ***/
#define GEN_STF(name, stop, opc, type) \
static void glue(gen_, name)(DisasContext *ctx) \
@@ -9984,6 +9998,7 @@ GEN_LDXF(name, ldop, 0x17, op | 0x00, type)
GEN_LDFS(lfd, ld64, 0x12, PPC_FLOAT)
GEN_LDFS(lfs, ld32fs, 0x10, PPC_FLOAT)
GEN_HANDLER_E(lfiwax, 0x1f, 0x17, 0x1a, 0x00000001, PPC_NONE, PPC2_ISA205),
+GEN_HANDLER_E(lfiwzx, 0x1f, 0x17, 0x1b, 0x1, PPC_NONE, PPC2_FP_CVT_ISA206),
GEN_HANDLER_E(lfdp, 0x39, 0xFF, 0xFF, 0x00200003, PPC_NONE, PPC2_ISA205),
GEN_HANDLER_E(lfdpx, 0x1F, 0x17, 0x18, 0x00200001, PPC_NONE, PPC2_ISA205),