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| author | blueswir1 <blueswir1@c046a42c-6fe2-441c-8c8c-71466251a162> | 2009-03-07 20:50:01 +0000 |
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| committer | blueswir1 <blueswir1@c046a42c-6fe2-441c-8c8c-71466251a162> | 2009-03-07 20:50:01 +0000 |
| commit | f6b868fc5899899774eecc43fc21b3a6c6ecfa9a (patch) | |
| tree | 00cf84e46ee8213d417d41e5cc61506d7d5f4ff8 /target-ppc/translate.c | |
| parent | c5e97233e8c8e53aab1b80b5e9891a71c4edea3e (diff) | |
| download | qemu-f6b868fc5899899774eecc43fc21b3a6c6ecfa9a.tar.gz | |
Implement slbmte
In order to modify SLB entries on recent PPC64 machines, the slbmte
instruction is used.
This patch implements the slbmte instruction and makes the "bridge"
mode code use the slb set functions, so we can move the SLB into
the CPU struct later.
This is required for Linux to run on PPC64.
Signed-off-by: Alexander Graf <alex@csgraf.de>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6747 c046a42c-6fe2-441c-8c8c-71466251a162
Diffstat (limited to 'target-ppc/translate.c')
| -rw-r--r-- | target-ppc/translate.c | 23 |
1 files changed, 19 insertions, 4 deletions
diff --git a/target-ppc/translate.c b/target-ppc/translate.c index 6816e0867d..cbf1a35899 100644 --- a/target-ppc/translate.c +++ b/target-ppc/translate.c @@ -4300,7 +4300,7 @@ GEN_HANDLER2(mfsr_64b, "mfsr", 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT_64B) return; } t0 = tcg_const_tl(SR(ctx->opcode)); - gen_helper_load_slb(cpu_gpr[rD(ctx->opcode)], t0); + gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], t0); tcg_temp_free(t0); #endif } @@ -4320,7 +4320,7 @@ GEN_HANDLER2(mfsrin_64b, "mfsrin", 0x1F, 0x13, 0x14, 0x001F0001, t0 = tcg_temp_new(); tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28); tcg_gen_andi_tl(t0, t0, 0xF); - gen_helper_load_slb(cpu_gpr[rD(ctx->opcode)], t0); + gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], t0); tcg_temp_free(t0); #endif } @@ -4337,7 +4337,7 @@ GEN_HANDLER2(mtsr_64b, "mtsr", 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT_64B) return; } t0 = tcg_const_tl(SR(ctx->opcode)); - gen_helper_store_slb(t0, cpu_gpr[rS(ctx->opcode)]); + gen_helper_store_sr(t0, cpu_gpr[rS(ctx->opcode)]); tcg_temp_free(t0); #endif } @@ -4357,10 +4357,25 @@ GEN_HANDLER2(mtsrin_64b, "mtsrin", 0x1F, 0x12, 0x07, 0x001F0001, t0 = tcg_temp_new(); tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28); tcg_gen_andi_tl(t0, t0, 0xF); - gen_helper_store_slb(t0, cpu_gpr[rS(ctx->opcode)]); + gen_helper_store_sr(t0, cpu_gpr[rS(ctx->opcode)]); tcg_temp_free(t0); #endif } + +/* slbmte */ +GEN_HANDLER2(slbmte, "slbmte", 0x1F, 0x12, 0x0C, 0x00000000, PPC_SEGMENT_64B) +{ +#if defined(CONFIG_USER_ONLY) + gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); +#else + if (unlikely(!ctx->mem_idx)) { + gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); + return; + } + gen_helper_store_slb(cpu_gpr[rB(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); +#endif +} + #endif /* defined(TARGET_PPC64) */ /*** Lookaside buffer management ***/ |