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| author | Blue Swirl <blauwirbel@gmail.com> | 2012-05-30 04:23:38 +0000 |
|---|---|---|
| committer | Alexander Graf <agraf@suse.de> | 2012-06-24 01:04:43 +0200 |
| commit | d523dd00a7d73b28f2e99acf45a4b3f92e56e40a (patch) | |
| tree | 15b832ce716b8fbcf340c37a78d01910fbde2e87 /target-ppc/translate.c | |
| parent | 901c4eaf9670060c837987dac7912e5ab46df58a (diff) | |
| download | qemu-d523dd00a7d73b28f2e99acf45a4b3f92e56e40a.tar.gz | |
ppc: Avoid AREG0 for misc helpers
Add an explicit CPUPPCState parameter instead of relying on AREG0.
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
Signed-off-by: Andreas Färber <afaerber@suse.de>
Signed-off-by: Alexander Graf <agraf@suse.de>
Diffstat (limited to 'target-ppc/translate.c')
| -rw-r--r-- | target-ppc/translate.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/target-ppc/translate.c b/target-ppc/translate.c index 5eec4b040b..bcc993313d 100644 --- a/target-ppc/translate.c +++ b/target-ppc/translate.c @@ -4551,7 +4551,7 @@ static void gen_abso(DisasContext *ctx) static void gen_clcs(DisasContext *ctx) { TCGv_i32 t0 = tcg_const_i32(rA(ctx->opcode)); - gen_helper_clcs(cpu_gpr[rD(ctx->opcode)], t0); + gen_helper_clcs(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); tcg_temp_free_i32(t0); /* Rc=1 sets CR0 to an undefined state */ } |