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authorDavid Gibson <david@gibson.dropbear.id.au>2013-04-07 19:08:20 +0000
committerAlexander Graf <agraf@suse.de>2013-04-26 23:02:41 +0200
commit702763fa322ea69dde92517735507e0ac3879b5d (patch)
tree13dff3f2861c111843819f8c4edcb952054f95e1 /target-ppc/translate_init.c
parent0cbad81f70546b58f08de3225f1eca7a8b869b09 (diff)
downloadqemu-702763fa322ea69dde92517735507e0ac3879b5d.tar.gz
target-ppc: Add more stubs for POWER7 PMU registers
In addition to the performance monitor registers found on nearly all 6xx chips, the POWER7 has two additional counters (PMC5 & PMC6) and an extra control register (MMCRA). This patch adds stub support for them to qemu - the registers won't do anything, but with this change won't cause illegal instruction traps accessing them. They're also registered with their ONE_REG ids, so their value will be kept in sync with KVM where appropriate. Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Alexander Graf <agraf@suse.de>
Diffstat (limited to 'target-ppc/translate_init.c')
-rw-r--r--target-ppc/translate_init.c12
1 files changed, 12 insertions, 0 deletions
diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
index 769f5fd65a..b0e3536e63 100644
--- a/target-ppc/translate_init.c
+++ b/target-ppc/translate_init.c
@@ -6977,6 +6977,18 @@ static void init_proc_POWER7 (CPUPPCState *env)
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
KVM_REG_PPC_DSCR, 0x00000000);
+ spr_register_kvm(env, SPR_MMCRA, "SPR_MMCRA",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ KVM_REG_PPC_MMCRA, 0x00000000);
+ spr_register_kvm(env, SPR_PMC5, "SPR_PMC5",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ KVM_REG_PPC_PMC5, 0x00000000);
+ spr_register_kvm(env, SPR_PMC6, "SPR_PMC6",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ KVM_REG_PPC_PMC6, 0x00000000);
#endif /* !CONFIG_USER_ONLY */
/* Memory management */
/* XXX : not implemented */