diff options
| author | Tom Musta <tommusta@gmail.com> | 2014-01-07 10:05:55 -0600 |
|---|---|---|
| committer | Alexander Graf <agraf@suse.de> | 2014-03-05 03:06:40 +0100 |
| commit | 1fa6c533047b4447cef693a1f54babc6a69fe19d (patch) | |
| tree | 7633ae9d94b372225ff73ec57b1075df943f0364 /target-ppc | |
| parent | a98eb9e99df4c11966fcd56cbcb6f06e6f413a89 (diff) | |
| download | qemu-1fa6c533047b4447cef693a1f54babc6a69fe19d.tar.gz | |
target-ppc: Add Flag for ISA2.06 Atomic Instructions
This patch adds a flag for the atomic instructions introduced
in Power ISA V2.06B.
Signed-off-by: Tom Musta <tommusta@gmail.com>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Alexander Graf <agraf@suse.de>
Diffstat (limited to 'target-ppc')
| -rw-r--r-- | target-ppc/cpu.h | 5 | ||||
| -rw-r--r-- | target-ppc/translate_init.c | 9 |
2 files changed, 10 insertions, 4 deletions
diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h index ab900a4343..bf2b64fd8c 100644 --- a/target-ppc/cpu.h +++ b/target-ppc/cpu.h @@ -1881,10 +1881,13 @@ enum { PPC2_PERM_ISA206 = 0x0000000000000080ULL, /* ISA 2.06B divide extended variants */ PPC2_DIVE_ISA206 = 0x0000000000000100ULL, + /* ISA 2.06B larx/stcx. instructions */ + PPC2_ATOMIC_ISA206 = 0x0000000000000200ULL, + #define PPC_TCG_INSNS2 (PPC2_BOOKE206 | PPC2_VSX | PPC2_PRCNTL | PPC2_DBRX | \ PPC2_ISA205 | PPC2_VSX207 | PPC2_PERM_ISA206 | \ - PPC2_DIVE_ISA206) + PPC2_DIVE_ISA206 | PPC2_ATOMIC_ISA206) }; /*****************************************************************************/ diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c index 76f326dc2a..abe0a2147f 100644 --- a/target-ppc/translate_init.c +++ b/target-ppc/translate_init.c @@ -7069,7 +7069,8 @@ POWERPC_FAMILY(POWER7)(ObjectClass *oc, void *data) PPC_SEGMENT_64B | PPC_SLBI | PPC_POPCNTB | PPC_POPCNTWD; pcc->insns_flags2 = PPC2_VSX | PPC2_DFP | PPC2_DBRX | PPC2_ISA205 | - PPC2_PERM_ISA206 | PPC2_DIVE_ISA206; + PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 | + PPC2_ATOMIC_ISA206; pcc->msr_mask = 0x800000000284FF37ULL; pcc->mmu_model = POWERPC_MMU_2_06; #if defined(CONFIG_SOFTMMU) @@ -7108,7 +7109,8 @@ POWERPC_FAMILY(POWER7P)(ObjectClass *oc, void *data) PPC_SEGMENT_64B | PPC_SLBI | PPC_POPCNTB | PPC_POPCNTWD; pcc->insns_flags2 = PPC2_VSX | PPC2_DFP | PPC2_DBRX | PPC2_ISA205 | - PPC2_PERM_ISA206 | PPC2_DIVE_ISA206; + PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 | + PPC2_ATOMIC_ISA206; pcc->msr_mask = 0x800000000204FF37ULL; pcc->mmu_model = POWERPC_MMU_2_06; #if defined(CONFIG_SOFTMMU) @@ -7147,7 +7149,8 @@ POWERPC_FAMILY(POWER8)(ObjectClass *oc, void *data) PPC_SEGMENT_64B | PPC_SLBI | PPC_POPCNTB | PPC_POPCNTWD; pcc->insns_flags2 = PPC2_VSX | PPC2_VSX207 | PPC2_DFP | PPC2_DBRX | - PPC2_PERM_ISA206 | PPC2_DIVE_ISA206; + PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 | + PPC2_ATOMIC_ISA206; pcc->msr_mask = 0x800000000284FF36ULL; pcc->mmu_model = POWERPC_MMU_2_06; #if defined(CONFIG_SOFTMMU) |