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| author | Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com> | 2014-02-20 18:52:31 +0100 |
|---|---|---|
| committer | Alexander Graf <agraf@suse.de> | 2014-03-05 03:07:02 +0100 |
| commit | 3f94170be35e3d15d63498e9f0beeee6775be47d (patch) | |
| tree | 306c848044fda36ebea2b4a40bc2d02bdec4ef85 /target-ppc | |
| parent | 7c43bca004afdb2a86c20ab3131ec1eb7a78d80d (diff) | |
| download | qemu-3f94170be35e3d15d63498e9f0beeee6775be47d.tar.gz | |
target-ppc: Change the hpte store API
For updating in kernel htab we need to provide both pte0 and pte1, hence update
the interface to take pte0 and pte1 together
Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>
[ ldq_phys() API change, Greg Kurz <gkurz@linux.vnet.ibm.com> ]
Signed-off-by: Greg Kurz <gkurz@linux.vnet.ibm.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
Diffstat (limited to 'target-ppc')
| -rw-r--r-- | target-ppc/mmu-hash64.c | 3 | ||||
| -rw-r--r-- | target-ppc/mmu-hash64.h | 24 |
2 files changed, 10 insertions, 17 deletions
diff --git a/target-ppc/mmu-hash64.c b/target-ppc/mmu-hash64.c index 68a6f69112..8dd5d22fa9 100644 --- a/target-ppc/mmu-hash64.c +++ b/target-ppc/mmu-hash64.c @@ -566,7 +566,8 @@ int ppc_hash64_handle_mmu_fault(CPUPPCState *env, target_ulong eaddr, } if (new_pte1 != pte.pte1) { - ppc_hash64_store_hpte1(env, pte_offset, new_pte1); + ppc_hash64_store_hpte(env, pte_offset / HASH_PTE_SIZE_64, + pte.pte0, new_pte1); } /* 7. Determine the real address from the PTE */ diff --git a/target-ppc/mmu-hash64.h b/target-ppc/mmu-hash64.h index e7cb96fe66..49d866b576 100644 --- a/target-ppc/mmu-hash64.h +++ b/target-ppc/mmu-hash64.h @@ -106,26 +106,18 @@ static inline target_ulong ppc_hash64_load_hpte1(CPUPPCState *env, } } -static inline void ppc_hash64_store_hpte0(CPUPPCState *env, - hwaddr pte_offset, target_ulong pte0) +static inline void ppc_hash64_store_hpte(CPUPPCState *env, + target_ulong pte_index, + target_ulong pte0, target_ulong pte1) { CPUState *cs = ENV_GET_CPU(env); + pte_index *= HASH_PTE_SIZE_64; if (env->external_htab) { - stq_p(env->external_htab + pte_offset, pte0); + stq_p(env->external_htab + pte_index, pte0); + stq_p(env->external_htab + pte_index + HASH_PTE_SIZE_64/2, pte1); } else { - stq_phys(cs->as, env->htab_base + pte_offset, pte0); - } -} - -static inline void ppc_hash64_store_hpte1(CPUPPCState *env, - hwaddr pte_offset, target_ulong pte1) -{ - CPUState *cs = ENV_GET_CPU(env); - if (env->external_htab) { - stq_p(env->external_htab + pte_offset + HASH_PTE_SIZE_64/2, pte1); - } else { - stq_phys(cs->as, - env->htab_base + pte_offset + HASH_PTE_SIZE_64/2, pte1); + stq_phys(cs->as, env->htab_base + pte_index, pte0); + stq_phys(cs->as, env->htab_base + pte_index + HASH_PTE_SIZE_64/2, pte1); } } |