diff options
| author | Tom Musta <tommusta@gmail.com> | 2014-01-07 10:05:50 -0600 |
|---|---|---|
| committer | Alexander Graf <agraf@suse.de> | 2014-03-05 03:06:38 +0100 |
| commit | a824bc191a90d86980a9ed090cb1d1219faaf8e7 (patch) | |
| tree | f55229b97709ac852cb4f2a1c97eda911abd8881 /target-ppc | |
| parent | 86ba37edcb6556b124840f04d180a34ffcc71086 (diff) | |
| download | qemu-a824bc191a90d86980a9ed090cb1d1219faaf8e7.tar.gz | |
target-ppc: Add Flag for ISA2.06 Divide Extended Instructions
This patch adds a flag for the Divide Extended instructions that
were introduced in Power ISA V2.06B. The flag is added to the
Power7 and Power8 models.
Signed-off-by: Tom Musta <tommusta@gmail.com>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Alexander Graf <agraf@suse.de>
Diffstat (limited to 'target-ppc')
| -rw-r--r-- | target-ppc/cpu.h | 5 | ||||
| -rw-r--r-- | target-ppc/translate_init.c | 6 |
2 files changed, 7 insertions, 4 deletions
diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h index 74ff4c6a65..ab900a4343 100644 --- a/target-ppc/cpu.h +++ b/target-ppc/cpu.h @@ -1879,9 +1879,12 @@ enum { PPC2_VSX207 = 0x0000000000000040ULL, /* ISA 2.06B bpermd */ PPC2_PERM_ISA206 = 0x0000000000000080ULL, + /* ISA 2.06B divide extended variants */ + PPC2_DIVE_ISA206 = 0x0000000000000100ULL, #define PPC_TCG_INSNS2 (PPC2_BOOKE206 | PPC2_VSX | PPC2_PRCNTL | PPC2_DBRX | \ - PPC2_ISA205 | PPC2_VSX207 | PPC2_PERM_ISA206) + PPC2_ISA205 | PPC2_VSX207 | PPC2_PERM_ISA206 | \ + PPC2_DIVE_ISA206) }; /*****************************************************************************/ diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c index 53fa4249db..76f326dc2a 100644 --- a/target-ppc/translate_init.c +++ b/target-ppc/translate_init.c @@ -7069,7 +7069,7 @@ POWERPC_FAMILY(POWER7)(ObjectClass *oc, void *data) PPC_SEGMENT_64B | PPC_SLBI | PPC_POPCNTB | PPC_POPCNTWD; pcc->insns_flags2 = PPC2_VSX | PPC2_DFP | PPC2_DBRX | PPC2_ISA205 | - PPC2_PERM_ISA206; + PPC2_PERM_ISA206 | PPC2_DIVE_ISA206; pcc->msr_mask = 0x800000000284FF37ULL; pcc->mmu_model = POWERPC_MMU_2_06; #if defined(CONFIG_SOFTMMU) @@ -7108,7 +7108,7 @@ POWERPC_FAMILY(POWER7P)(ObjectClass *oc, void *data) PPC_SEGMENT_64B | PPC_SLBI | PPC_POPCNTB | PPC_POPCNTWD; pcc->insns_flags2 = PPC2_VSX | PPC2_DFP | PPC2_DBRX | PPC2_ISA205 | - PPC2_PERM_ISA206; + PPC2_PERM_ISA206 | PPC2_DIVE_ISA206; pcc->msr_mask = 0x800000000204FF37ULL; pcc->mmu_model = POWERPC_MMU_2_06; #if defined(CONFIG_SOFTMMU) @@ -7147,7 +7147,7 @@ POWERPC_FAMILY(POWER8)(ObjectClass *oc, void *data) PPC_SEGMENT_64B | PPC_SLBI | PPC_POPCNTB | PPC_POPCNTWD; pcc->insns_flags2 = PPC2_VSX | PPC2_VSX207 | PPC2_DFP | PPC2_DBRX | - PPC2_PERM_ISA206; + PPC2_PERM_ISA206 | PPC2_DIVE_ISA206; pcc->msr_mask = 0x800000000284FF36ULL; pcc->mmu_model = POWERPC_MMU_2_06; #if defined(CONFIG_SOFTMMU) |