diff options
| author | Aurelien Jarno <aurelien@aurel32.net> | 2011-01-06 15:38:18 +0100 |
|---|---|---|
| committer | Aurelien Jarno <aurelien@aurel32.net> | 2011-01-06 16:10:54 +0100 |
| commit | 3eb28bbd472c0d4e3182421c4af7043afa059903 (patch) | |
| tree | a765dc3354e6c107240316568866ab4d354cd767 /target-ppc | |
| parent | dd94ad96e51457d8d9562a73659734b559d2f4b1 (diff) | |
| download | qemu-3eb28bbd472c0d4e3182421c4af7043afa059903.tar.gz | |
target-ppc: fix default qNaN
On PPC the default qNaN doesn't have the sign bit set.
Acked-by: Alexander Graf <agraf@suse.de>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Diffstat (limited to 'target-ppc')
| -rw-r--r-- | target-ppc/op_helper.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/target-ppc/op_helper.c b/target-ppc/op_helper.c index 31520ab639..c69ffc96b1 100644 --- a/target-ppc/op_helper.c +++ b/target-ppc/op_helper.c @@ -643,7 +643,7 @@ static inline uint64_t fload_invalid_op_excp(int op) env->fpscr &= ~((1 << FPSCR_FR) | (1 << FPSCR_FI)); if (ve == 0) { /* Set the result to quiet NaN */ - ret = 0xFFF8000000000000ULL; + ret = 0x7FF8000000000000ULL; env->fpscr &= ~(0xF << FPSCR_FPCC); env->fpscr |= 0x11 << FPSCR_FPCC; } @@ -654,7 +654,7 @@ static inline uint64_t fload_invalid_op_excp(int op) env->fpscr &= ~((1 << FPSCR_FR) | (1 << FPSCR_FI)); if (ve == 0) { /* Set the result to quiet NaN */ - ret = 0xFFF8000000000000ULL; + ret = 0x7FF8000000000000ULL; env->fpscr &= ~(0xF << FPSCR_FPCC); env->fpscr |= 0x11 << FPSCR_FPCC; } |