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authorbellard <bellard@c046a42c-6fe2-441c-8c8c-71466251a162>2004-04-25 17:57:43 +0000
committerbellard <bellard@c046a42c-6fe2-441c-8c8c-71466251a162>2004-04-25 17:57:43 +0000
commitd720b93d0bcfe1beb729245b9ed1e5f071a24bd5 (patch)
tree4f9d65b82b9eb8bd65681cfde6bb18e7b6bd2eae /target-ppc
parenteeab3a558f89e30ee93ef628bcbd6a3f64b9b8a6 (diff)
downloadqemu-d720b93d0bcfe1beb729245b9ed1e5f071a24bd5.tar.gz
precise self modifying code support
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@745 c046a42c-6fe2-441c-8c8c-71466251a162
Diffstat (limited to 'target-ppc')
-rw-r--r--target-ppc/cpu.h7
1 files changed, 7 insertions, 0 deletions
diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h
index 6cd08950f4..e6cb0946d7 100644
--- a/target-ppc/cpu.h
+++ b/target-ppc/cpu.h
@@ -164,6 +164,13 @@ typedef struct CPUPPCState {
int user_mode_only; /* user mode only simulation */
struct TranslationBlock *current_tb; /* currently executing TB */
/* soft mmu support */
+ /* in order to avoid passing too many arguments to the memory
+ write helpers, we store some rarely used information in the CPU
+ context) */
+ unsigned long mem_write_pc; /* host pc at which the memory was
+ written */
+ unsigned long mem_write_vaddr; /* target virtual addr at which the
+ memory was written */
/* 0 = kernel, 1 = user (may have 2 = kernel code, 3 = user code ?) */
CPUTLBEntry tlb_read[2][CPU_TLB_SIZE];
CPUTLBEntry tlb_write[2][CPU_TLB_SIZE];