diff options
| author | Benjamin Herrenschmidt <benh@kernel.crashing.org> | 2016-03-21 13:52:39 +0100 |
|---|---|---|
| committer | David Gibson <david@gibson.dropbear.id.au> | 2016-03-24 11:17:34 +1100 |
| commit | eb5ceb4d389b1b34b210baf9fa49b48bacb2538b (patch) | |
| tree | bb66952a6a3d82b02fc0090e53c95a0528e85b81 /target-ppc | |
| parent | a6eabb9e5908ddf521ea372651b8321ffa804bd8 (diff) | |
| download | qemu-eb5ceb4d389b1b34b210baf9fa49b48bacb2538b.tar.gz | |
ppc: Add dummy CIABR SPR
We should implement HW breakpoint/watchpoint, qemu supports them...
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Diffstat (limited to 'target-ppc')
| -rw-r--r-- | target-ppc/cpu.h | 1 | ||||
| -rw-r--r-- | target-ppc/translate_init.c | 5 |
2 files changed, 6 insertions, 0 deletions
diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h index a3c4fb112a..29c48600d9 100644 --- a/target-ppc/cpu.h +++ b/target-ppc/cpu.h @@ -1393,6 +1393,7 @@ static inline int cpu_mmu_index (CPUPPCState *env, bool ifetch) #define SPR_PSPB (0x09F) #define SPR_DAWR (0x0B4) #define SPR_RPR (0x0BA) +#define SPR_CIABR (0x0BB) #define SPR_DAWRX (0x0BC) #define SPR_HFSCR (0x0BE) #define SPR_VRSAVE (0x100) diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c index bd62e3be02..37c4fb5302 100644 --- a/target-ppc/translate_init.c +++ b/target-ppc/translate_init.c @@ -7589,6 +7589,11 @@ static void gen_spr_book3s_207_dbg(CPUPPCState *env) SPR_NOACCESS, SPR_NOACCESS, &spr_read_generic, &spr_write_generic, KVM_REG_PPC_DAWRX, 0x00000000); + spr_register_kvm_hv(env, SPR_CIABR, "CIABR", + SPR_NOACCESS, SPR_NOACCESS, + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + KVM_REG_PPC_CIABR, 0x00000000); } static void gen_spr_970_dbg(CPUPPCState *env) |