diff options
| author | Benjamin Herrenschmidt <benh@kernel.crashing.org> | 2016-07-27 16:56:48 +1000 |
|---|---|---|
| committer | David Gibson <david@gibson.dropbear.id.au> | 2016-09-07 12:40:11 +1000 |
| commit | 5817355ed0d989c72713d89c8d1e9133ec376485 (patch) | |
| tree | 80d0168c955920bc6b145431efbd6c752c8c96c2 /target-ppc | |
| parent | 65f2475f1f3b46086dfeef9ba882ea3d9d909d57 (diff) | |
| download | qemu-5817355ed0d989c72713d89c8d1e9133ec376485.tar.gz | |
ppc: load/store multiple and string insns don't do LE
Just generate an alignment interrupt
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Diffstat (limited to 'target-ppc')
| -rw-r--r-- | target-ppc/translate.c | 29 |
1 files changed, 29 insertions, 0 deletions
diff --git a/target-ppc/translate.c b/target-ppc/translate.c index 1315656448..379d3d46c4 100644 --- a/target-ppc/translate.c +++ b/target-ppc/translate.c @@ -2889,6 +2889,11 @@ static void gen_lmw(DisasContext *ctx) { TCGv t0; TCGv_i32 t1; + + if (ctx->le_mode) { + gen_align_no_le(ctx); + return; + } gen_set_access_type(ctx, ACCESS_INT); t0 = tcg_temp_new(); t1 = tcg_const_i32(rD(ctx->opcode)); @@ -2903,6 +2908,11 @@ static void gen_stmw(DisasContext *ctx) { TCGv t0; TCGv_i32 t1; + + if (ctx->le_mode) { + gen_align_no_le(ctx); + return; + } gen_set_access_type(ctx, ACCESS_INT); t0 = tcg_temp_new(); t1 = tcg_const_i32(rS(ctx->opcode)); @@ -2929,6 +2939,10 @@ static void gen_lswi(DisasContext *ctx) int ra = rA(ctx->opcode); int nr; + if (ctx->le_mode) { + gen_align_no_le(ctx); + return; + } if (nb == 0) nb = 32; nr = (nb + 3) / 4; @@ -2952,6 +2966,11 @@ static void gen_lswx(DisasContext *ctx) { TCGv t0; TCGv_i32 t1, t2, t3; + + if (ctx->le_mode) { + gen_align_no_le(ctx); + return; + } gen_set_access_type(ctx, ACCESS_INT); t0 = tcg_temp_new(); gen_addr_reg_index(ctx, t0); @@ -2971,6 +2990,11 @@ static void gen_stswi(DisasContext *ctx) TCGv t0; TCGv_i32 t1, t2; int nb = NB(ctx->opcode); + + if (ctx->le_mode) { + gen_align_no_le(ctx); + return; + } gen_set_access_type(ctx, ACCESS_INT); t0 = tcg_temp_new(); gen_addr_register(ctx, t0); @@ -2989,6 +3013,11 @@ static void gen_stswx(DisasContext *ctx) { TCGv t0; TCGv_i32 t1, t2; + + if (ctx->le_mode) { + gen_align_no_le(ctx); + return; + } gen_set_access_type(ctx, ACCESS_INT); t0 = tcg_temp_new(); gen_addr_reg_index(ctx, t0); |