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| author | Cornelia Huck <cornelia.huck@de.ibm.com> | 2015-10-08 15:05:46 +0200 |
|---|---|---|
| committer | Cornelia Huck <cornelia.huck@de.ibm.com> | 2015-10-20 16:21:00 +0200 |
| commit | b080364aedfc294c53c4c4af255efcf007b35d9d (patch) | |
| tree | 00312ba0d2ad1a97a4964edf8b2fcb959ae7ec19 /target-s390x/cpu.h | |
| parent | 2ab75df38e34fe9bc271b5115ab52114e6e63a89 (diff) | |
| download | qemu-b080364aedfc294c53c4c4af255efcf007b35d9d.tar.gz | |
s390x: flagify mcic values
Instead of using magic values when building the machine check
interruption code, add some defines as by chapter 11-14 in the PoP.
This should make it easier to catch problems like the missing vector
register validity bit ("s390x/kvm: Fix vector validity bit in device
machine checks"), and less hassle should we want to generate machine
checks beyond the channel reports we currently support.
Acked-by: David Hildenbrand <dahi@linux.vnet.ibm.com>
Signed-off-by: Cornelia Huck <cornelia.huck@de.ibm.com>
Diffstat (limited to 'target-s390x/cpu.h')
| -rw-r--r-- | target-s390x/cpu.h | 45 |
1 files changed, 45 insertions, 0 deletions
diff --git a/target-s390x/cpu.h b/target-s390x/cpu.h index e4de8632f3..07ae16c8c5 100644 --- a/target-s390x/cpu.h +++ b/target-s390x/cpu.h @@ -1275,4 +1275,49 @@ static inline bool vregs_needed(void *opaque) return 0; } #endif + +/* machine check interruption code */ + +/* subclasses */ +#define MCIC_SC_SD 0x8000000000000000ULL +#define MCIC_SC_PD 0x4000000000000000ULL +#define MCIC_SC_SR 0x2000000000000000ULL +#define MCIC_SC_CD 0x0800000000000000ULL +#define MCIC_SC_ED 0x0400000000000000ULL +#define MCIC_SC_DG 0x0100000000000000ULL +#define MCIC_SC_W 0x0080000000000000ULL +#define MCIC_SC_CP 0x0040000000000000ULL +#define MCIC_SC_SP 0x0020000000000000ULL +#define MCIC_SC_CK 0x0010000000000000ULL + +/* subclass modifiers */ +#define MCIC_SCM_B 0x0002000000000000ULL +#define MCIC_SCM_DA 0x0000000020000000ULL +#define MCIC_SCM_AP 0x0000000000080000ULL + +/* storage errors */ +#define MCIC_SE_SE 0x0000800000000000ULL +#define MCIC_SE_SC 0x0000400000000000ULL +#define MCIC_SE_KE 0x0000200000000000ULL +#define MCIC_SE_DS 0x0000100000000000ULL +#define MCIC_SE_IE 0x0000000080000000ULL + +/* validity bits */ +#define MCIC_VB_WP 0x0000080000000000ULL +#define MCIC_VB_MS 0x0000040000000000ULL +#define MCIC_VB_PM 0x0000020000000000ULL +#define MCIC_VB_IA 0x0000010000000000ULL +#define MCIC_VB_FA 0x0000008000000000ULL +#define MCIC_VB_VR 0x0000004000000000ULL +#define MCIC_VB_EC 0x0000002000000000ULL +#define MCIC_VB_FP 0x0000001000000000ULL +#define MCIC_VB_GR 0x0000000800000000ULL +#define MCIC_VB_CR 0x0000000400000000ULL +#define MCIC_VB_ST 0x0000000100000000ULL +#define MCIC_VB_AR 0x0000000040000000ULL +#define MCIC_VB_PR 0x0000000000200000ULL +#define MCIC_VB_FC 0x0000000000100000ULL +#define MCIC_VB_CT 0x0000000000020000ULL +#define MCIC_VB_CC 0x0000000000010000ULL + #endif |