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| author | Richard Henderson <rth@twiddle.net> | 2012-08-22 13:00:27 -0700 |
|---|---|---|
| committer | Richard Henderson <rth@twiddle.net> | 2013-01-05 12:18:39 -0800 |
| commit | 97c3ab61c46c1c0194657b8bead3d499600d8aab (patch) | |
| tree | 39ce57c70e3c8c5dd1c25da8cc24fcf49bcfca6a /target-s390x | |
| parent | 4f7403d52b1c682df15c862f5e7ca0712b66089f (diff) | |
| download | qemu-97c3ab61c46c1c0194657b8bead3d499600d8aab.tar.gz | |
target-s390: Convert MVCP, MVCS
Signed-off-by: Richard Henderson <rth@twiddle.net>
Diffstat (limited to 'target-s390x')
| -rw-r--r-- | target-s390x/insn-data.def | 4 | ||||
| -rw-r--r-- | target-s390x/translate.c | 49 |
2 files changed, 27 insertions, 26 deletions
diff --git a/target-s390x/insn-data.def b/target-s390x/insn-data.def index ff8f57fe2b..65f0bfd768 100644 --- a/target-s390x/insn-data.def +++ b/target-s390x/insn-data.def @@ -461,6 +461,10 @@ C(0x8300, DIAG, RX_a, Z, 0, 0, 0, 0, diag, 0) /* LOAD PSW */ C(0x8200, LPSW, S, Z, 0, a2, 0, 0, lpsw, 0) +/* MOVE TO PRIMARY */ + C(0xda00, MVCP, SS_d, Z, la1, a2, 0, 0, mvcp, 0) +/* MOVE TO SECONDARY */ + C(0xdb00, MVCS, SS_d, Z, la1, a2, 0, 0, mvcs, 0) /* SET ADDRESSING MODE */ /* We only do 64-bit, so accept this as a no-op. Let SAM24 and SAM31 signal illegal instruction. */ diff --git a/target-s390x/translate.c b/target-s390x/translate.c index 8a7cfafb9f..070da1e817 100644 --- a/target-s390x/translate.c +++ b/target-s390x/translate.c @@ -2001,7 +2001,7 @@ static void disas_s390_insn(CPUS390XState *env, DisasContext *s) TCGv_i32 tmp32_1, tmp32_2; unsigned char opc; uint64_t insn; - int op, r1, r2, r3, d1, d2, x2, b1, b2, r1b; + int op, r1, r2, r3, d2, x2, b2, r1b; opc = cpu_ldub_code(env, s->pc); LOG_DISAS("opc 0x%x\n", opc); @@ -2139,31 +2139,6 @@ static void disas_s390_insn(CPUS390XState *env, DisasContext *s) tcg_temp_free_i32(tmp32_1); tcg_temp_free_i32(tmp32_2); break; -#ifndef CONFIG_USER_ONLY - case 0xda: /* MVCP D1(R1,B1),D2(B2),R3 [SS] */ - case 0xdb: /* MVCS D1(R1,B1),D2(B2),R3 [SS] */ - check_privileged(s); - potential_page_fault(s); - insn = ld_code6(env, s->pc); - r1 = (insn >> 36) & 0xf; - r3 = (insn >> 32) & 0xf; - b1 = (insn >> 28) & 0xf; - d1 = (insn >> 16) & 0xfff; - b2 = (insn >> 12) & 0xf; - d2 = insn & 0xfff; - /* XXX key in r3 */ - tmp = get_address(s, 0, b1, d1); - tmp2 = get_address(s, 0, b2, d2); - if (opc == 0xda) { - gen_helper_mvcp(cc_op, cpu_env, regs[r1], tmp, tmp2); - } else { - gen_helper_mvcs(cc_op, cpu_env, regs[r1], tmp, tmp2); - } - set_cc_static(s); - tcg_temp_free_i64(tmp); - tcg_temp_free_i64(tmp2); - break; -#endif case 0xe3: insn = ld_code6(env, s->pc); debug_insn(insn); @@ -3111,6 +3086,28 @@ static ExitStatus op_mvcle(DisasContext *s, DisasOps *o) return NO_EXIT; } +#ifndef CONFIG_USER_ONLY +static ExitStatus op_mvcp(DisasContext *s, DisasOps *o) +{ + int r1 = get_field(s->fields, l1); + check_privileged(s); + potential_page_fault(s); + gen_helper_mvcp(cc_op, cpu_env, regs[r1], o->addr1, o->in2); + set_cc_static(s); + return NO_EXIT; +} + +static ExitStatus op_mvcs(DisasContext *s, DisasOps *o) +{ + int r1 = get_field(s->fields, l1); + check_privileged(s); + potential_page_fault(s); + gen_helper_mvcs(cc_op, cpu_env, regs[r1], o->addr1, o->in2); + set_cc_static(s); + return NO_EXIT; +} +#endif + static ExitStatus op_mul(DisasContext *s, DisasOps *o) { tcg_gen_mul_i64(o->out, o->in1, o->in2); |