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| author | Aurelien Jarno <aurelien@aurel32.net> | 2010-02-03 02:32:49 +0100 |
|---|---|---|
| committer | Aurelien Jarno <aurelien@aurel32.net> | 2010-02-09 21:08:05 +0100 |
| commit | af090497c6bd692864f49b4214d56dd4203c9f34 (patch) | |
| tree | 92a00ac54b14141a3ffbd58f99aee2633625671f /target-sh4/cpu.h | |
| parent | 628b61a0727e240be911ba9d01b41c58841b2c43 (diff) | |
| download | qemu-af090497c6bd692864f49b4214d56dd4203c9f34.tar.gz | |
target-sh4: MMU: reduce the size of a TLB entry
Reduce the size of the TLB entry from 32 to 16 bytes, reorganising
members and using a bit field.
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Diffstat (limited to 'target-sh4/cpu.h')
| -rw-r--r-- | target-sh4/cpu.h | 23 |
1 files changed, 11 insertions, 12 deletions
diff --git a/target-sh4/cpu.h b/target-sh4/cpu.h index 015d59845a..85f221d978 100644 --- a/target-sh4/cpu.h +++ b/target-sh4/cpu.h @@ -72,21 +72,20 @@ * The use of DELAY_SLOT_TRUE flag makes us accept such SR_T modification. */ -/* XXXXX The structure could be made more compact */ typedef struct tlb_t { - uint8_t asid; /* address space identifier */ uint32_t vpn; /* virtual page number */ - uint8_t v; /* validity */ uint32_t ppn; /* physical page number */ - uint8_t sz; /* page size */ - uint32_t size; /* cached page size in bytes */ - uint8_t sh; /* share status */ - uint8_t c; /* cacheability */ - uint8_t pr; /* protection key */ - uint8_t d; /* dirty */ - uint8_t wt; /* write through */ - uint8_t sa; /* space attribute (PCMCIA) */ - uint8_t tc; /* timing control */ + uint32_t size; /* mapped page size in bytes */ + uint8_t asid; /* address space identifier */ + uint8_t v:1; /* validity */ + uint8_t sz:2; /* page size */ + uint8_t sh:1; /* share status */ + uint8_t c:1; /* cacheability */ + uint8_t pr:2; /* protection key */ + uint8_t d:1; /* dirty */ + uint8_t wt:1; /* write through */ + uint8_t sa:3; /* space attribute (PCMCIA) */ + uint8_t tc:1; /* timing control */ } tlb_t; #define UTLB_SIZE 64 |