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| author | Aurelien Jarno <aurelien@aurel32.net> | 2011-01-09 23:53:45 +0100 |
|---|---|---|
| committer | Aurelien Jarno <aurelien@aurel32.net> | 2011-01-09 23:59:12 +0100 |
| commit | c0f809c46aa271f29a9e6268cdeda1f21301a8ef (patch) | |
| tree | 01dcf7fa000ec9d9b73610a7d3a6599b198ace1f /target-sh4/cpu.h | |
| parent | 759c90ba3d4f8dcb748d7719f7ea82b181ffd590 (diff) | |
| download | qemu-c0f809c46aa271f29a9e6268cdeda1f21301a8ef.tar.gz | |
target-sh4: implement writes to mmaped ITLB
Some Linux kernels seems to implement ITLB/UTLB flushing through by
writing all TLB entries through the memory mapped interface instead
of writing one to MMUCR.TI.
Implement memory mapped ITLB write interface so that such kernels can
boot. This fixes https://bugs.launchpad.net/bugs/700774 .
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Diffstat (limited to 'target-sh4/cpu.h')
| -rw-r--r-- | target-sh4/cpu.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/target-sh4/cpu.h b/target-sh4/cpu.h index e19776643b..8ccf25cafb 100644 --- a/target-sh4/cpu.h +++ b/target-sh4/cpu.h @@ -172,6 +172,8 @@ void do_interrupt(CPUSH4State * env); void sh4_cpu_list(FILE *f, fprintf_function cpu_fprintf); #if !defined(CONFIG_USER_ONLY) void cpu_sh4_invalidate_tlb(CPUSH4State *s); +void cpu_sh4_write_mmaped_itlb_addr(CPUSH4State *s, target_phys_addr_t addr, + uint32_t mem_value); void cpu_sh4_write_mmaped_utlb_addr(CPUSH4State *s, target_phys_addr_t addr, uint32_t mem_value); #endif |