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| author | ths <ths@c046a42c-6fe2-441c-8c8c-71466251a162> | 2007-06-22 11:12:01 +0000 |
|---|---|---|
| committer | ths <ths@c046a42c-6fe2-441c-8c8c-71466251a162> | 2007-06-22 11:12:01 +0000 |
| commit | ea6cf6be8e078cbe87f0e3fe226e3afdd92505e0 (patch) | |
| tree | 3fcaac4e7c1f3c855493b7afe41cd4bc463a62b4 /target-sh4/cpu.h | |
| parent | 6db45e6519fee264ef3bbe88f50233f23640b403 (diff) | |
| download | qemu-ea6cf6be8e078cbe87f0e3fe226e3afdd92505e0.tar.gz | |
Emulate more fpu opcodes, by Magnus Damm.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3002 c046a42c-6fe2-441c-8c8c-71466251a162
Diffstat (limited to 'target-sh4/cpu.h')
| -rw-r--r-- | target-sh4/cpu.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/target-sh4/cpu.h b/target-sh4/cpu.h index 4f25b6cafa..5290dd2642 100644 --- a/target-sh4/cpu.h +++ b/target-sh4/cpu.h @@ -99,6 +99,7 @@ typedef struct CPUSH4State { /* temporary float registers */ float32 ft0, ft1; float64 dt0, dt1; + float_status fp_status; /* Those belong to the specific unit (SH7750) but are handled here */ uint32_t mmucr; /* MMU control register */ |