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| author | Andreas Färber <afaerber@suse.de> | 2013-06-29 04:18:45 +0200 |
|---|---|---|
| committer | Andreas Färber <afaerber@suse.de> | 2013-07-27 00:04:17 +0200 |
| commit | 5b50e790f9e9403d11b4164193b76530ee85a2a1 (patch) | |
| tree | 63244f49c1b53b05d1d8ddc795643e376dd55971 /target-sh4/gdbstub.c | |
| parent | 986a2998932e978e63fc3b7ead1fef81f7aad52e (diff) | |
| download | qemu-5b50e790f9e9403d11b4164193b76530ee85a2a1.tar.gz | |
cpu: Introduce CPUClass::gdb_{read,write}_register()
Completes migration of target-specific code to new target-*/gdbstub.c.
Acked-by: Michael Walle <michael@walle.cc> (for lm32)
Acked-by: Max Filippov <jcmvbkbc@gmail.com> (for xtensa)
Signed-off-by: Andreas Färber <afaerber@suse.de>
Diffstat (limited to 'target-sh4/gdbstub.c')
| -rw-r--r-- | target-sh4/gdbstub.c | 13 |
1 files changed, 11 insertions, 2 deletions
diff --git a/target-sh4/gdbstub.c b/target-sh4/gdbstub.c index fb85718fc0..df4fa2af76 100644 --- a/target-sh4/gdbstub.c +++ b/target-sh4/gdbstub.c @@ -17,12 +17,18 @@ * You should have received a copy of the GNU Lesser General Public * License along with this library; if not, see <http://www.gnu.org/licenses/>. */ +#include "config.h" +#include "qemu-common.h" +#include "exec/gdbstub.h" /* Hint: Use "set architecture sh4" in GDB to see fpu registers */ /* FIXME: We should use XML for this. */ -static int cpu_gdb_read_register(CPUSH4State *env, uint8_t *mem_buf, int n) +int superh_cpu_gdb_read_register(CPUState *cs, uint8_t *mem_buf, int n) { + SuperHCPU *cpu = SUPERH_CPU(cs); + CPUSH4State *env = &cpu->env; + switch (n) { case 0 ... 7: if ((env->sr & (SR_MD | SR_RB)) == (SR_MD | SR_RB)) { @@ -70,8 +76,11 @@ static int cpu_gdb_read_register(CPUSH4State *env, uint8_t *mem_buf, int n) return 0; } -static int cpu_gdb_write_register(CPUSH4State *env, uint8_t *mem_buf, int n) +int superh_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n) { + SuperHCPU *cpu = SUPERH_CPU(cs); + CPUSH4State *env = &cpu->env; + switch (n) { case 0 ... 7: if ((env->sr & (SR_MD | SR_RB)) == (SR_MD | SR_RB)) { |