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| author | Aurelien Jarno <aurelien@aurel32.net> | 2011-01-13 08:20:39 +0100 |
|---|---|---|
| committer | Aurelien Jarno <aurelien@aurel32.net> | 2011-01-16 13:19:20 +0100 |
| commit | b2d9eda5d473fa7251319a368b0ee72d75218aed (patch) | |
| tree | 72f57871efe63fd03f00ffcde050b1475a37fa39 /target-sh4/translate.c | |
| parent | 2411fde9a41323310d472dd352006989f30049b2 (diff) | |
| download | qemu-b2d9eda5d473fa7251319a368b0ee72d75218aed.tar.gz | |
target-sh4: implement negc using TCG
Using setcond it's now possible to generate a relatively short negc
instruction in TCG.
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Diffstat (limited to 'target-sh4/translate.c')
| -rw-r--r-- | target-sh4/translate.c | 16 |
1 files changed, 15 insertions, 1 deletions
diff --git a/target-sh4/translate.c b/target-sh4/translate.c index 743d76a575..35573be5ff 100644 --- a/target-sh4/translate.c +++ b/target-sh4/translate.c @@ -952,7 +952,21 @@ static void _decode_opc(DisasContext * ctx) tcg_gen_neg_i32(REG(B11_8), REG(B7_4)); return; case 0x600a: /* negc Rm,Rn */ - gen_helper_negc(REG(B11_8), REG(B7_4)); + { + TCGv t0, t1; + t0 = tcg_temp_new(); + tcg_gen_neg_i32(t0, REG(B7_4)); + t1 = tcg_temp_new(); + tcg_gen_andi_i32(t1, cpu_sr, SR_T); + tcg_gen_sub_i32(REG(B11_8), t0, t1); + tcg_gen_andi_i32(cpu_sr, cpu_sr, ~SR_T); + tcg_gen_setcond_i32(TCG_COND_GE, t1, REG(B11_8), t0); + tcg_gen_or_i32(cpu_sr, cpu_sr, t1); + tcg_gen_setcondi_i32(TCG_COND_GE, t1, t0, 0); + tcg_gen_or_i32(cpu_sr, cpu_sr, t1); + tcg_temp_free(t0); + tcg_temp_free(t1); + } return; case 0x6007: /* not Rm,Rn */ tcg_gen_not_i32(REG(B11_8), REG(B7_4)); |