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| author | Fabien Chouteau <chouteau@adacore.com> | 2011-01-24 12:56:56 +0100 |
|---|---|---|
| committer | Blue Swirl <blauwirbel@gmail.com> | 2011-01-24 20:54:34 +0000 |
| commit | 4a2ba232843ac4197c586c1f0f0adbb1eb02fe34 (patch) | |
| tree | d24803cef3f9de4140d0b7f599a44675e68e468a /target-sparc/cpu.h | |
| parent | b04d98905400aeb7dd62ce938d7eecddf2816817 (diff) | |
| download | qemu-4a2ba232843ac4197c586c1f0f0adbb1eb02fe34.tar.gz | |
SPARC: Add asr17 register support
This register is activated by CPU_FEATURE_ASR17 in the feature field.
Signed-off-by: Fabien Chouteau <chouteau@adacore.com>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
Diffstat (limited to 'target-sparc/cpu.h')
| -rw-r--r-- | target-sparc/cpu.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/target-sparc/cpu.h b/target-sparc/cpu.h index 5c50d9e535..6f5990b130 100644 --- a/target-sparc/cpu.h +++ b/target-sparc/cpu.h @@ -267,6 +267,7 @@ typedef struct sparc_def_t { #define CPU_FEATURE_CMT (1 << 12) #define CPU_FEATURE_GL (1 << 13) #define CPU_FEATURE_TA0_SHUTDOWN (1 << 14) /* Shutdown on "ta 0x0" */ +#define CPU_FEATURE_ASR17 (1 << 15) #ifndef TARGET_SPARC64 #define CPU_DEFAULT_FEATURES (CPU_FEATURE_FLOAT | CPU_FEATURE_SWAP | \ CPU_FEATURE_MUL | CPU_FEATURE_DIV | \ |