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| author | Igor V. Kovalenko <igor.v.kovalenko@gmail.com> | 2010-05-22 14:52:35 +0400 |
|---|---|---|
| committer | Blue Swirl <blauwirbel@gmail.com> | 2010-05-22 12:51:48 +0000 |
| commit | 9fd1ae3a0e3328056eaa2ae950ba0023e53423b2 (patch) | |
| tree | a502557fbb90efc2bb6ba2acddf1fbdfef598337 /target-sparc/cpu.h | |
| parent | e21295860883e0e1f8acc352f21eb9563b5cfd40 (diff) | |
| download | qemu-9fd1ae3a0e3328056eaa2ae950ba0023e53423b2.tar.gz | |
sparc64: fix mmu context at trap levels above zero
- cpu_mmu_index return MMU_NUCLEUS_IDX if trap level is not zero
- cpu_get_tb_cpu_state: store trap level and primary context in flags
this allows to restart code translation when address translation is changed
- stop translation block after writing to pstate and tl registers
- stop translation block after writing to alternate space
this can be optimized to stop only if address translation can be changed
by write operation (e.g. by comparing with MMU ASI values)
Signed-off-by: Igor V. Kovalenko <igor.v.kovalenko@gmail.com>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
Diffstat (limited to 'target-sparc/cpu.h')
| -rw-r--r-- | target-sparc/cpu.h | 14 |
1 files changed, 10 insertions, 4 deletions
diff --git a/target-sparc/cpu.h b/target-sparc/cpu.h index 4fd58e9c38..8f0484b24a 100644 --- a/target-sparc/cpu.h +++ b/target-sparc/cpu.h @@ -556,7 +556,9 @@ static inline int cpu_mmu_index(CPUState *env1) #elif !defined(TARGET_SPARC64) return env1->psrs; #else - if (cpu_hypervisor_mode(env1)) { + if (env1->tl > 0) { + return MMU_NUCLEUS_IDX; + } else if (cpu_hypervisor_mode(env1)) { return MMU_HYPV_IDX; } else if (cpu_supervisor_mode(env1)) { return MMU_KERNEL_IDX; @@ -636,9 +638,13 @@ static inline void cpu_get_tb_cpu_state(CPUState *env, target_ulong *pc, *cs_base = env->npc; #ifdef TARGET_SPARC64 // AM . Combined FPU enable bits . PRIV . DMMU enabled . IMMU enabled - *flags = ((env->pstate & PS_AM) << 2) - | (((env->pstate & PS_PEF) >> 1) | ((env->fprs & FPRS_FEF) << 2)) - | (env->pstate & PS_PRIV) | ((env->lsu & (DMMU_E | IMMU_E)) >> 2); + *flags = ((env->pstate & PS_AM) << 2) /* 5 */ + | (((env->pstate & PS_PEF) >> 1) /* 3 */ + | ((env->fprs & FPRS_FEF) << 2)) /* 4 */ + | (env->pstate & PS_PRIV) /* 2 */ + | ((env->lsu & (DMMU_E | IMMU_E)) >> 2) /* 1, 0 */ + | ((env->tl & 0xff) << 8) + | (env->dmmu.mmu_primary_context << 16); /* 16... */ #else // FPU enable . Supervisor *flags = (env->psref << 4) | env->psrs; |