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| author | Tsuneo Saito <tsnsaito@gmail.com> | 2011-07-22 00:16:33 +0900 |
|---|---|---|
| committer | Blue Swirl <blauwirbel@gmail.com> | 2011-07-21 20:02:22 +0000 |
| commit | d1afc48b7cfdb4490f322d5d82a2aae6d545ec06 (patch) | |
| tree | 02865832c18da733cf4f094f700bf81b66547ae2 /target-sparc/cpu.h | |
| parent | b7785d2072164fa8576767853af9ed517508ee57 (diff) | |
| download | qemu-d1afc48b7cfdb4490f322d5d82a2aae6d545ec06.tar.gz | |
SPARC64: implement addtional MMU faults related to nonfaulting load
This patch implements MMU faults caused by TTE.NFO and TTE.E:
- access other than nonfaulting load to a page marked NFO should
raise data_access_exception
- nonfaulting load to a page marked with E bit should raise
data_access_exception
To distinguish nonfaulting loads, this patch extends (abuses?) the rw
argument of get_physical_address_data(). rw is set to 4 on nonfaulting
loads.
Signed-off-by: Tsuneo Saito <tsnsaito@gmail.com>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
Diffstat (limited to 'target-sparc/cpu.h')
| -rw-r--r-- | target-sparc/cpu.h | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/target-sparc/cpu.h b/target-sparc/cpu.h index f4eeff5b17..a51863cf07 100644 --- a/target-sparc/cpu.h +++ b/target-sparc/cpu.h @@ -290,15 +290,19 @@ enum { #endif #define TTE_VALID_BIT (1ULL << 63) +#define TTE_NFO_BIT (1ULL << 60) #define TTE_USED_BIT (1ULL << 41) #define TTE_LOCKED_BIT (1ULL << 6) +#define TTE_SIDEEFFECT_BIT (1ULL << 3) #define TTE_PRIV_BIT (1ULL << 2) #define TTE_W_OK_BIT (1ULL << 1) #define TTE_GLOBAL_BIT (1ULL << 0) #define TTE_IS_VALID(tte) ((tte) & TTE_VALID_BIT) +#define TTE_IS_NFO(tte) ((tte) & TTE_NFO_BIT) #define TTE_IS_USED(tte) ((tte) & TTE_USED_BIT) #define TTE_IS_LOCKED(tte) ((tte) & TTE_LOCKED_BIT) +#define TTE_IS_SIDEEFFECT(tte) ((tte) & TTE_SIDEEFFECT_BIT) #define TTE_IS_PRIV(tte) ((tte) & TTE_PRIV_BIT) #define TTE_IS_W_OK(tte) ((tte) & TTE_W_OK_BIT) #define TTE_IS_GLOBAL(tte) ((tte) & TTE_GLOBAL_BIT) |