diff options
| author | Igor V. Kovalenko <igor.v.kovalenko@gmail.com> | 2010-01-07 23:28:31 +0300 |
|---|---|---|
| committer | Blue Swirl <blauwirbel@gmail.com> | 2010-01-08 17:25:13 +0000 |
| commit | d532b26c9dee0fb5b2186572f921b1e413963ec2 (patch) | |
| tree | 75eef4cbe9034f96b98c176db0e8eeb03923f652 /target-sparc/cpu.h | |
| parent | 2df6c2d0de31461f18d97f8a4d122bdb003297db (diff) | |
| download | qemu-d532b26c9dee0fb5b2186572f921b1e413963ec2.tar.gz | |
sparc64: interrupt trap handling
cpu_check_irqs
- handle SOFTINT register TICK and STICK timer bits
- only check interrupt levels greater than PIL value
- handle preemption by higher level traps
cpu_exec
- handle CPU_INTERRUPT_HARD only if interrupts are enabled
- PIL 15 is not special level on sparcv9
Signed-off-by: Igor V. Kovalenko <igor.v.kovalenko@gmail.com>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
Diffstat (limited to 'target-sparc/cpu.h')
| -rw-r--r-- | target-sparc/cpu.h | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/target-sparc/cpu.h b/target-sparc/cpu.h index e5b282d391..50859c7f1f 100644 --- a/target-sparc/cpu.h +++ b/target-sparc/cpu.h @@ -577,6 +577,16 @@ static inline int cpu_interrupts_enabled(CPUState *env1) return 0; } +static inline int cpu_pil_allowed(CPUState *env1, int pil) +{ +#if !defined(TARGET_SPARC64) + /* level 15 is non-maskable on sparc v8 */ + return pil == 15 || pil > env1->psrpil; +#else + return pil > env1->psrpil; +#endif +} + static inline int cpu_fpu_enabled(CPUState *env1) { #if defined(CONFIG_USER_ONLY) |