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| author | blueswir1 <blueswir1@c046a42c-6fe2-441c-8c8c-71466251a162> | 2008-12-23 15:30:50 +0000 |
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| committer | blueswir1 <blueswir1@c046a42c-6fe2-441c-8c8c-71466251a162> | 2008-12-23 15:30:50 +0000 |
| commit | 4017190e2d75882a0e9dbc40f403e584e0ab46c4 (patch) | |
| tree | 8fa9cec975d8f2afd8449ca08947177326afc442 /target-sparc/cpu.h | |
| parent | 0bb3602c44b73c647b8a478d7077192a576b5781 (diff) | |
| download | qemu-4017190e2d75882a0e9dbc40f403e584e0ab46c4.tar.gz | |
Add SuperSPARC MMU breakpoint registers (Robert Reif)
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6125 c046a42c-6fe2-441c-8c8c-71466251a162
Diffstat (limited to 'target-sparc/cpu.h')
| -rw-r--r-- | target-sparc/cpu.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/target-sparc/cpu.h b/target-sparc/cpu.h index 136319c5c4..1fb249b65a 100644 --- a/target-sparc/cpu.h +++ b/target-sparc/cpu.h @@ -301,6 +301,7 @@ typedef struct CPUSPARCState { uint32_t mmuregs[32]; uint64_t mxccdata[4]; uint64_t mxccregs[8]; + uint64_t mmubpregs[4]; uint64_t prom_addr; #endif /* temporary float registers */ |