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| author | blueswir1 <blueswir1@c046a42c-6fe2-441c-8c8c-71466251a162> | 2008-02-11 18:27:33 +0000 |
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| committer | blueswir1 <blueswir1@c046a42c-6fe2-441c-8c8c-71466251a162> | 2008-02-11 18:27:33 +0000 |
| commit | 3deaeab717e8632c0c1825b566c92aceaf8c4c75 (patch) | |
| tree | 9bbbcd3786516352e41138d06e5abdc345d42952 /target-sparc/cpu.h | |
| parent | 5228c2d3b40d976f451831a8a8b3092c37f44747 (diff) | |
| download | qemu-3deaeab717e8632c0c1825b566c92aceaf8c4c75.tar.gz | |
Sparc32 MMU register fixes (Robert Reif)
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3979 c046a42c-6fe2-441c-8c8c-71466251a162
Diffstat (limited to 'target-sparc/cpu.h')
| -rw-r--r-- | target-sparc/cpu.h | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/target-sparc/cpu.h b/target-sparc/cpu.h index 6f95d94699..e0715a1a70 100644 --- a/target-sparc/cpu.h +++ b/target-sparc/cpu.h @@ -198,6 +198,10 @@ typedef struct CPUSPARCState { int interrupt_request; int halted; uint32_t mmu_bm; + uint32_t mmu_ctpr_mask; + uint32_t mmu_cxr_mask; + uint32_t mmu_sfsr_mask; + uint32_t mmu_trcr_mask; /* NOTE: we allow 8 more registers to handle wrapping */ target_ulong regbase[NWINDOWS * 16 + 8]; |