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| author | Igor V. Kovalenko <igor.v.kovalenko@gmail.com> | 2010-05-03 11:29:44 +0400 |
|---|---|---|
| committer | Blue Swirl <blauwirbel@gmail.com> | 2010-05-06 23:14:26 +0300 |
| commit | 2065061ede22d401aae2ce995c3af54db9d28639 (patch) | |
| tree | 14413bbc4636f37834e8570928f94220d4d853a4 /target-sparc/cpu.h | |
| parent | 299b520cd4092be3c53f8380b81315c33927d9d3 (diff) | |
| download | qemu-2065061ede22d401aae2ce995c3af54db9d28639.tar.gz | |
sparc64: handle asi referencing nucleus and secondary MMU contexts
- increase max supported MMU modes to 6
- handle nucleus context asi
- handle secondary context asi
- handle non-faulting loads from secondary context
Signed-off-by: Igor V. Kovalenko <igor.v.kovalenko@gmail.com>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
Diffstat (limited to 'target-sparc/cpu.h')
| -rw-r--r-- | target-sparc/cpu.h | 13 |
1 files changed, 12 insertions, 1 deletions
diff --git a/target-sparc/cpu.h b/target-sparc/cpu.h index b7057282b8..b67933381c 100644 --- a/target-sparc/cpu.h +++ b/target-sparc/cpu.h @@ -224,7 +224,7 @@ enum { #if !defined(TARGET_SPARC64) #define NB_MMU_MODES 2 #else -#define NB_MMU_MODES 3 +#define NB_MMU_MODES 6 typedef struct trap_state { uint64_t tpc; uint64_t tnpc; @@ -571,6 +571,9 @@ static inline void PUT_CWP64(CPUSPARCState *env1, int cwp) #if !defined(CONFIG_USER_ONLY) void do_unassigned_access(target_phys_addr_t addr, int is_write, int is_exec, int is_asi, int size); +target_phys_addr_t cpu_get_phys_page_nofault(CPUState *env, target_ulong addr, + int mmu_idx); + #endif int cpu_sparc_signal_handler(int host_signum, void *pinfo, void *puc); @@ -587,10 +590,18 @@ int cpu_sparc_signal_handler(int host_signum, void *pinfo, void *puc); #define MMU_MODE1_SUFFIX _kernel #ifdef TARGET_SPARC64 #define MMU_MODE2_SUFFIX _hypv +#define MMU_MODE3_SUFFIX _nucleus +#define MMU_MODE4_SUFFIX _user_secondary +#define MMU_MODE5_SUFFIX _kernel_secondary #endif #define MMU_USER_IDX 0 #define MMU_KERNEL_IDX 1 #define MMU_HYPV_IDX 2 +#ifdef TARGET_SPARC64 +#define MMU_NUCLEUS_IDX 3 +#define MMU_USER_SECONDARY_IDX 4 +#define MMU_KERNEL_SECONDARY_IDX 5 +#endif static inline int cpu_mmu_index(CPUState *env1) { |