diff options
| author | Fabien Chouteau <chouteau@adacore.com> | 2011-01-24 12:56:56 +0100 |
|---|---|---|
| committer | Blue Swirl <blauwirbel@gmail.com> | 2011-01-24 20:54:34 +0000 |
| commit | 4a2ba232843ac4197c586c1f0f0adbb1eb02fe34 (patch) | |
| tree | d24803cef3f9de4140d0b7f599a44675e68e468a /target-sparc/translate.c | |
| parent | b04d98905400aeb7dd62ce938d7eecddf2816817 (diff) | |
| download | qemu-4a2ba232843ac4197c586c1f0f0adbb1eb02fe34.tar.gz | |
SPARC: Add asr17 register support
This register is activated by CPU_FEATURE_ASR17 in the feature field.
Signed-off-by: Fabien Chouteau <chouteau@adacore.com>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
Diffstat (limited to 'target-sparc/translate.c')
| -rw-r--r-- | target-sparc/translate.c | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/target-sparc/translate.c b/target-sparc/translate.c index dff0f19f70..e26462eef5 100644 --- a/target-sparc/translate.c +++ b/target-sparc/translate.c @@ -2067,6 +2067,17 @@ static void disas_sparc_insn(DisasContext * dc) case 0x10 ... 0x1f: /* implementation-dependent in the SPARCv8 manual, rdy on the microSPARC II */ + /* Read Asr17 */ + if (rs1 == 0x11 && dc->def->features & CPU_FEATURE_ASR17) { + TCGv r_const; + + /* Read Asr17 for a Leon3 monoprocessor */ + r_const = tcg_const_tl((1 << 8) + | (dc->def->nwindows - 1)); + gen_movl_TN_reg(rd, r_const); + tcg_temp_free(r_const); + break; + } #endif gen_movl_TN_reg(rd, cpu_y); break; |