diff options
| author | bellard <bellard@c046a42c-6fe2-441c-8c8c-71466251a162> | 2004-01-05 00:06:41 +0000 |
|---|---|---|
| committer | bellard <bellard@c046a42c-6fe2-441c-8c8c-71466251a162> | 2004-01-05 00:06:41 +0000 |
| commit | bd497938895ec4fd7b327aac4de390e34f543509 (patch) | |
| tree | a6b475e982c15cc90e5524f833f7a34ebd601e13 /target-sparc | |
| parent | 16d17fdb8ee6b25c501b1d32a74cf187455fe3d7 (diff) | |
| download | qemu-bd497938895ec4fd7b327aac4de390e34f543509.tar.gz | |
use generic GenOpFunc
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@543 c046a42c-6fe2-441c-8c8c-71466251a162
Diffstat (limited to 'target-sparc')
| -rw-r--r-- | target-sparc/translate.c | 30 |
1 files changed, 4 insertions, 26 deletions
diff --git a/target-sparc/translate.c b/target-sparc/translate.c index a5c1dbe6f3..82bd33c8e7 100644 --- a/target-sparc/translate.c +++ b/target-sparc/translate.c @@ -2,6 +2,7 @@ SPARC translation Copyright (C) 2003 Thomas M. Ogrisegg <tom@fnord.at> + Copyright (C) 2003 Fabrice Bellard This library is free software; you can redistribute it and/or modify it under the terms of the GNU Lesser General Public @@ -19,33 +20,15 @@ */ /* - SPARC has two pitfalls: Delay slots and (a)nullification. - This is currently solved as follows: - - 'call' instructions simply execute the delay slot before the actual - control transfer instructions. - - 'jmpl' instructions execute calculate the destination, then execute - the delay slot and then do the control transfer. - - (conditional) branch instructions are the most difficult ones, as the - delay slot may be nullified (ie. not executed). This happens when a - conditional branch is not executed (thus no control transfer happens) - and the 'anull' bit in the branch instruction opcode is set. This is - currently solved by doing a jump after the delay slot instruction. - TODO-list: - Register window overflow/underflow check + NPC/PC static optimisations (use JUMP_TB when possible) FPU-Instructions - Coprocessor-Instructions - Check signedness issues Privileged instructions + Coprocessor-Instructions Optimize synthetic instructions Optional alignment and privileged instruction check - - -- TMO, 09/03/03 - */ +*/ #include <stdarg.h> #include <stdlib.h> @@ -87,11 +70,6 @@ enum { static void disas_sparc_insn(DisasContext * dc); -typedef void (GenOpFunc) (void); -typedef void (GenOpFunc1) (long); -typedef void (GenOpFunc2) (long, long); -typedef void (GenOpFunc3) (long, long, long); - static GenOpFunc *gen_op_movl_TN_reg[2][32] = { { gen_op_movl_g0_T0, |