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| author | ths <ths@c046a42c-6fe2-441c-8c8c-71466251a162> | 2007-02-02 01:03:34 +0000 |
|---|---|---|
| committer | ths <ths@c046a42c-6fe2-441c-8c8c-71466251a162> | 2007-02-02 01:03:34 +0000 |
| commit | 01d6a890b4dbfa63a6c2e23a768f0e6c9bee55e0 (patch) | |
| tree | 2f88fc70593a1e65ccdb76554be5484a8410102f /target-sparc | |
| parent | 6a1cbf68b7cbb6967f218a2cf65345518b49706a (diff) | |
| download | qemu-01d6a890b4dbfa63a6c2e23a768f0e6c9bee55e0.tar.gz | |
Sparc arm/mips/sparc register patch, by Martin Bochnig.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2377 c046a42c-6fe2-441c-8c8c-71466251a162
Diffstat (limited to 'target-sparc')
| -rw-r--r-- | target-sparc/exec.h | 22 |
1 files changed, 22 insertions, 0 deletions
diff --git a/target-sparc/exec.h b/target-sparc/exec.h index 1b67ef4bf6..6e0515f6e9 100644 --- a/target-sparc/exec.h +++ b/target-sparc/exec.h @@ -3,23 +3,41 @@ #include "dyngen-exec.h" #include "config.h" +#if defined(__sparc__) +struct CPUSPARCState *env; +#else register struct CPUSPARCState *env asm(AREG0); +#endif + #ifdef TARGET_SPARC64 #define T0 (env->t0) #define T1 (env->t1) #define T2 (env->t2) #define REGWPTR env->regwptr #else +#if defined(__sparc__) +register uint32_t T0 asm(AREG3); +register uint32_t T1 asm(AREG2); +#else register uint32_t T0 asm(AREG1); register uint32_t T1 asm(AREG2); +#endif #undef REG_REGWPTR // Broken #ifdef REG_REGWPTR +#if defined(__sparc__) +register uint32_t *REGWPTR asm(AREG4); +#else register uint32_t *REGWPTR asm(AREG3); +#endif #define reg_REGWPTR #ifdef AREG4 +#if defined(__sparc__) +register uint32_t T2 asm(AREG0); +#else register uint32_t T2 asm(AREG4); +#endif #define reg_T2 #else #define T2 (env->t2) @@ -27,7 +45,11 @@ register uint32_t T2 asm(AREG4); #else #define REGWPTR env->regwptr +#if defined(__sparc__) +register uint32_t T2 asm(AREG0); +#else register uint32_t T2 asm(AREG3); +#endif #define reg_T2 #endif #endif |