diff options
| author | bellard <bellard@c046a42c-6fe2-441c-8c8c-71466251a162> | 2005-03-13 17:01:47 +0000 |
|---|---|---|
| committer | bellard <bellard@c046a42c-6fe2-441c-8c8c-71466251a162> | 2005-03-13 17:01:47 +0000 |
| commit | 7a0e1f41ceeb658791a1456ffc7f8f9edca7da19 (patch) | |
| tree | eab50fb37085ad2dc6e8aa283f334defd538fa8c /target-sparc | |
| parent | 4ecc31906d7535c4ad88fcc63968bef412dd67ba (diff) | |
| download | qemu-7a0e1f41ceeb658791a1456ffc7f8f9edca7da19.tar.gz | |
soft float support
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@1336 c046a42c-6fe2-441c-8c8c-71466251a162
Diffstat (limited to 'target-sparc')
| -rw-r--r-- | target-sparc/cpu.h | 3 | ||||
| -rw-r--r-- | target-sparc/op_helper.c | 18 |
2 files changed, 12 insertions, 9 deletions
diff --git a/target-sparc/cpu.h b/target-sparc/cpu.h index b07e2afcf4..67a6e3e465 100644 --- a/target-sparc/cpu.h +++ b/target-sparc/cpu.h @@ -15,6 +15,8 @@ #include "cpu-defs.h" +#include "softfloat.h" + /*#define EXCP_INTERRUPT 0x100*/ /* trap definitions */ @@ -150,6 +152,7 @@ typedef struct CPUSPARCState { /* temporary float registers */ float ft0, ft1, ft2; double dt0, dt1, dt2; + float_status fp_status; #if defined(TARGET_SPARC64) target_ulong t0, t1, t2; #endif diff --git a/target-sparc/op_helper.c b/target-sparc/op_helper.c index 9cb3de49ac..40ab90156e 100644 --- a/target-sparc/op_helper.c +++ b/target-sparc/op_helper.c @@ -1,5 +1,3 @@ -#include <math.h> -#include <fenv.h> #include "exec.h" //#define DEBUG_MMU @@ -24,17 +22,17 @@ void do_fitod(void) void do_fabss(void) { - FT0 = fabsf(FT1); + FT0 = float32_abs(FT1); } void do_fsqrts(void) { - FT0 = sqrtf(FT1); + FT0 = float32_sqrt(FT1, &env->fp_status); } void do_fsqrtd(void) { - DT0 = sqrt(DT1); + DT0 = float64_sqrt(DT1, &env->fp_status); } void do_fcmps (void) @@ -252,20 +250,22 @@ void helper_rett() void helper_ldfsr(void) { + int rnd_mode; switch (env->fsr & FSR_RD_MASK) { case FSR_RD_NEAREST: - fesetround(FE_TONEAREST); + rnd_mode = float_round_nearest_even; break; case FSR_RD_ZERO: - fesetround(FE_TOWARDZERO); + rnd_mode = float_round_to_zero; break; case FSR_RD_POS: - fesetround(FE_UPWARD); + rnd_mode = float_round_up; break; case FSR_RD_NEG: - fesetround(FE_DOWNWARD); + rnd_mode = float_round_down; break; } + set_float_rounding_mode(rnd_mode, &env->fp_status); } void cpu_get_fp64(uint64_t *pmant, uint16_t *pexp, double f) |