diff options
| author | Bastian Koppelmann <kbastian@mail.uni-paderborn.de> | 2015-02-25 11:55:52 +0000 |
|---|---|---|
| committer | Bastian Koppelmann <kbastian@mail.uni-paderborn.de> | 2015-03-16 15:44:48 +0000 |
| commit | 068fac77c81b5d227903d0b7ecd108edff4eb0eb (patch) | |
| tree | 52042b0430e1bfa0f9f41bc1652c0645985167ca /target-tricore/tricore-opcodes.h | |
| parent | 62e47b2e6d17020b78a676e086bf98cfeba595b7 (diff) | |
| download | qemu-068fac77c81b5d227903d0b7ecd108edff4eb0eb.tar.gz | |
target-tricore: Add instructions of RRR1 opcode format, which have 0xe3 as first opcode
Add helpers helper_subadr_h/_ssov which subs one halfword and adds one
halfword, rounds / and saturates each half word independently.
Add microcode helper functions:
* gen_msubad_h/ads_h: multiply two halfwords left justified and sub from the
first one word and add the second one word
/ and saturate each resulting word independetly.
* gen_msubadm_h/adms_h: multiply two halfwords in q-format left justified
and sub from the first one word and add to
the second one word / and saturate each resulting
word independetly.
* gen_msubadr32_h/32s_h: multiply two halfwords in q-format left justified
and sub from the first one word and add to
the second one word, round both results / and
saturate each resulting word independetly.
Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Diffstat (limited to 'target-tricore/tricore-opcodes.h')
| -rw-r--r-- | target-tricore/tricore-opcodes.h | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/target-tricore/tricore-opcodes.h b/target-tricore/tricore-opcodes.h index 80e17539d6..d3a9bc158b 100644 --- a/target-tricore/tricore-opcodes.h +++ b/target-tricore/tricore-opcodes.h @@ -523,7 +523,7 @@ enum { OPCM_32_RRR1_MADDSU_H = 0xc3, OPCM_32_RRR1_MSUB_H = 0xa3, OPCM_32_RRR1_MSUB_Q = 0x63, - OPCM_32_RRR1_MSUBADS_H = 0xe3, + OPCM_32_RRR1_MSUBAD_H = 0xe3, /* RRR2 Format */ OPCM_32_RRR2_MADD = 0x03, OPCM_32_RRR2_MSUB = 0x23, @@ -1352,7 +1352,7 @@ enum { OPC2_32_RRR1_MSUBADMS_H_64_LL = 0x3e, OPC2_32_RRR1_MSUBADMS_H_64_LU = 0x3d, OPC2_32_RRR1_MSUBADMS_H_64_UL = 0x3c, - OPC2_32_RRR1_MSUBADMS_H_16_UU = 0x3f, + OPC2_32_RRR1_MSUBADMS_H_64_UU = 0x3f, OPC2_32_RRR1_MSUBADR_H_16_LL = 0x0e, OPC2_32_RRR1_MSUBADR_H_16_LU = 0x0d, OPC2_32_RRR1_MSUBADR_H_16_UL = 0x0c, |