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| author | Bastian Koppelmann <kbastian@mail.uni-paderborn.de> | 2015-01-21 16:16:01 +0000 |
|---|---|---|
| committer | Bastian Koppelmann <kbastian@mail.uni-paderborn.de> | 2015-01-26 19:56:45 +0000 |
| commit | 40a1f64b468ee247fca3b237f0b89f066e59626c (patch) | |
| tree | f53e296b0266496348e46350e04f66a47e02b132 /target-tricore | |
| parent | 811ea608e9721dc4f6933da440f235e7d3a39c0f (diff) | |
| download | qemu-40a1f64b468ee247fca3b237f0b89f066e59626c.tar.gz | |
target-tricore: Fix bugs found by coverity
This fixes one bug and one false positive found by coverity. The bug is,
that gen_mtcr was missing a mask to check the flag, which resulted in dead code.
The false positive is a intentional missing break for a jump and link address
insn followed by a jump and link insn. This adds a fall through comment to avoid
the false positive in the future.
Reported-by: Markus Armbruster <armbru@redhat.com>
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Diffstat (limited to 'target-tricore')
| -rw-r--r-- | target-tricore/cpu.h | 1 | ||||
| -rw-r--r-- | target-tricore/translate.c | 3 |
2 files changed, 3 insertions, 1 deletions
diff --git a/target-tricore/cpu.h b/target-tricore/cpu.h index 7555b70a47..e5409e45f3 100644 --- a/target-tricore/cpu.h +++ b/target-tricore/cpu.h @@ -238,6 +238,7 @@ struct CPUTriCoreState { #define MASK_LCX_LCXS 0x000f0000 #define MASK_LCX_LCX0 0x0000ffff +#define TRICORE_HFLAG_KUU 0x3 #define TRICORE_HFLAG_UM0 0x00002 /* user mode-0 flag */ #define TRICORE_HFLAG_UM1 0x00001 /* user mode-1 flag */ #define TRICORE_HFLAG_SM 0x00000 /* kernel mode flag */ diff --git a/target-tricore/translate.c b/target-tricore/translate.c index 61518f3e52..57949fa6c6 100644 --- a/target-tricore/translate.c +++ b/target-tricore/translate.c @@ -343,7 +343,7 @@ static inline void gen_mfcr(CPUTriCoreState *env, TCGv ret, int32_t offset) static inline void gen_mtcr(CPUTriCoreState *env, DisasContext *ctx, TCGv r1, int32_t offset) { - if (ctx->hflags & TRICORE_HFLAG_SM) { + if ((ctx->hflags & TRICORE_HFLAG_KUU) == TRICORE_HFLAG_SM) { /* since we're caching PSW make this a special case */ if (offset == 0xfe04) { gen_helper_psw_write(cpu_env, r1); @@ -1647,6 +1647,7 @@ static void gen_compute_branch(DisasContext *ctx, uint32_t opc, int r1, break; case OPC1_32_B_JLA: tcg_gen_movi_tl(cpu_gpr_a[11], ctx->next_pc); + /* fall through */ case OPC1_32_B_JA: gen_goto_tb(ctx, 0, EA_B_ABSOLUT(offset)); break; |