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| author | Max Filippov <jcmvbkbc@gmail.com> | 2012-12-05 07:15:20 +0400 |
|---|---|---|
| committer | Blue Swirl <blauwirbel@gmail.com> | 2012-12-08 18:48:26 +0000 |
| commit | fcc803d119a4c01a9b0ee5bda35fda1eeabffa33 (patch) | |
| tree | bbd6697bd198b45b2322e5b43d3ab5159e093d98 /target-xtensa/cpu.c | |
| parent | 536b558f5896ebbd635b57fa393e82faaa32ad52 (diff) | |
| download | qemu-fcc803d119a4c01a9b0ee5bda35fda1eeabffa33.tar.gz | |
target-xtensa: implement ATOMCTL SR
ATOMCTL SR controls s32c1i opcode behavior depending on targeted memory
type. See ISA, 4.3.12.4 for details.
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
Diffstat (limited to 'target-xtensa/cpu.c')
| -rw-r--r-- | target-xtensa/cpu.c | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/target-xtensa/cpu.c b/target-xtensa/cpu.c index 9d01983d44..c6aa45ee6f 100644 --- a/target-xtensa/cpu.c +++ b/target-xtensa/cpu.c @@ -48,6 +48,8 @@ static void xtensa_cpu_reset(CPUState *s) XTENSA_OPTION_INTERRUPT) ? 0x1f : 0x10; env->sregs[VECBASE] = env->config->vecbase; env->sregs[IBREAKENABLE] = 0; + env->sregs[ATOMCTL] = xtensa_option_enabled(env->config, + XTENSA_OPTION_ATOMCTL) ? 0x28 : 0x15; env->pending_irq_level = 0; reset_mmu(env); |