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| author | Max Filippov <jcmvbkbc@gmail.com> | 2012-12-05 07:15:23 +0400 |
|---|---|---|
| committer | Blue Swirl <blauwirbel@gmail.com> | 2012-12-08 18:48:26 +0000 |
| commit | 53593e90d13264dc88b3281ddf75ceaa641df05a (patch) | |
| tree | 1012b37c8cf0e93b93130060cddbb8d4f7028f6b /target-xtensa/cpu.h | |
| parent | fe0bd475aa31e60674f7f53b85dc293108026202 (diff) | |
| download | qemu-53593e90d13264dc88b3281ddf75ceaa641df05a.tar.gz | |
target-xtensa: better control rsr/wsr/xsr access to SRs
There are read-only (DEBUGCAUSE, PRID) and write-only (INTCLEAR) SRs,
and INTERRUPT/INTSET SR allows rsr/wsr, but not xsr. Raise illeagal
opcode exception on illegal access to these SRs.
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
Diffstat (limited to 'target-xtensa/cpu.h')
0 files changed, 0 insertions, 0 deletions