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| author | Max Filippov <jcmvbkbc@gmail.com> | 2011-10-16 02:56:01 +0400 |
|---|---|---|
| committer | Blue Swirl <blauwirbel@gmail.com> | 2011-10-16 10:39:27 +0000 |
| commit | 7f65f4b059c4a91b97a032801a4c137e87612c6a (patch) | |
| tree | f024b50602cd1739fa82c23d6d868879f177a80d /target-xtensa/cpu.h | |
| parent | 3aeaea654afb1b45a99798f87c143392b2994712 (diff) | |
| download | qemu-7f65f4b059c4a91b97a032801a4c137e87612c6a.tar.gz | |
target-xtensa: increase xtensa options accuracy
- add separate options for each operation in the MISC_OP;
- add an option for MULSH/MULUH;
- put S32C1I under conditional store option.
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
Diffstat (limited to 'target-xtensa/cpu.h')
| -rw-r--r-- | target-xtensa/cpu.h | 6 |
1 files changed, 5 insertions, 1 deletions
diff --git a/target-xtensa/cpu.h b/target-xtensa/cpu.h index b43e565254..df168d5790 100644 --- a/target-xtensa/cpu.h +++ b/target-xtensa/cpu.h @@ -52,9 +52,13 @@ enum { XTENSA_OPTION_EXTENDED_L32R, XTENSA_OPTION_16_BIT_IMUL, XTENSA_OPTION_32_BIT_IMUL, + XTENSA_OPTION_32_BIT_IMUL_HIGH, XTENSA_OPTION_32_BIT_IDIV, XTENSA_OPTION_MAC16, - XTENSA_OPTION_MISC_OP, + XTENSA_OPTION_MISC_OP_NSA, + XTENSA_OPTION_MISC_OP_MINMAX, + XTENSA_OPTION_MISC_OP_SEXT, + XTENSA_OPTION_MISC_OP_CLAMPS, XTENSA_OPTION_COPROCESSOR, XTENSA_OPTION_BOOLEAN, XTENSA_OPTION_FP_COPROCESSOR, |