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| author | Max Filippov <jcmvbkbc@gmail.com> | 2012-12-05 07:15:20 +0400 |
|---|---|---|
| committer | Blue Swirl <blauwirbel@gmail.com> | 2012-12-08 18:48:26 +0000 |
| commit | fcc803d119a4c01a9b0ee5bda35fda1eeabffa33 (patch) | |
| tree | bbd6697bd198b45b2322e5b43d3ab5159e093d98 /target-xtensa/cpu.h | |
| parent | 536b558f5896ebbd635b57fa393e82faaa32ad52 (diff) | |
| download | qemu-fcc803d119a4c01a9b0ee5bda35fda1eeabffa33.tar.gz | |
target-xtensa: implement ATOMCTL SR
ATOMCTL SR controls s32c1i opcode behavior depending on targeted memory
type. See ISA, 4.3.12.4 for details.
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
Diffstat (limited to 'target-xtensa/cpu.h')
| -rw-r--r-- | target-xtensa/cpu.h | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/target-xtensa/cpu.h b/target-xtensa/cpu.h index 74e98883bf..d240ab70d9 100644 --- a/target-xtensa/cpu.h +++ b/target-xtensa/cpu.h @@ -65,6 +65,7 @@ enum { XTENSA_OPTION_FP_COPROCESSOR, XTENSA_OPTION_MP_SYNCHRO, XTENSA_OPTION_CONDITIONAL_STORE, + XTENSA_OPTION_ATOMCTL, /* Interrupts and exceptions */ XTENSA_OPTION_EXCEPTION, @@ -128,6 +129,7 @@ enum { ITLBCFG = 91, DTLBCFG = 92, IBREAKENABLE = 96, + ATOMCTL = 99, IBREAKA = 128, DBREAKA = 144, DBREAKC = 160, @@ -193,6 +195,14 @@ enum { #define REGION_PAGE_MASK 0xe0000000 +#define PAGE_CACHE_MASK 0x700 +#define PAGE_CACHE_SHIFT 8 +#define PAGE_CACHE_INVALID 0x000 +#define PAGE_CACHE_BYPASS 0x100 +#define PAGE_CACHE_WT 0x200 +#define PAGE_CACHE_WB 0x400 +#define PAGE_CACHE_ISOLATE 0x600 + enum { /* Static vectors */ EXC_RESET, |