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| author | Andreas Färber <afaerber@suse.de> | 2013-06-28 23:18:47 +0200 |
|---|---|---|
| committer | Andreas Färber <afaerber@suse.de> | 2013-07-26 23:23:54 +0200 |
| commit | a0e372f0c49ac01faeaeb73a6e8f50e8ac615f34 (patch) | |
| tree | 0a87f5f9ab3ff51ef996c69ded7cfa8f97768e92 /target-xtensa/helper.c | |
| parent | 19a77215f1ba966c4d37dadec45f38be789b8529 (diff) | |
| download | qemu-a0e372f0c49ac01faeaeb73a6e8f50e8ac615f34.tar.gz | |
cpu: Introduce CPUState::gdb_num_regs and CPUClass::gdb_num_core_regs
CPUState::gdb_num_regs replaces num_g_regs.
CPUClass::gdb_num_core_regs replaces NUM_CORE_REGS.
Allows building gdb_register_coprocessor() for xtensa, too.
As a side effect this should fix coprocessor register numbering for SMP.
Acked-by: Michael Walle <michael@walle.cc> (for lm32)
Acked-by: Max Filippov <jcmvbkbc@gmail.com> (for xtensa)
Signed-off-by: Andreas Färber <afaerber@suse.de>
Diffstat (limited to 'target-xtensa/helper.c')
| -rw-r--r-- | target-xtensa/helper.c | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/target-xtensa/helper.c b/target-xtensa/helper.c index e3098798af..a0f9993b2d 100644 --- a/target-xtensa/helper.c +++ b/target-xtensa/helper.c @@ -37,10 +37,18 @@ static struct XtensaConfigList *xtensa_cores; static void xtensa_core_class_init(ObjectClass *oc, void *data) { + CPUClass *cc = CPU_CLASS(oc); XtensaCPUClass *xcc = XTENSA_CPU_CLASS(oc); const XtensaConfig *config = data; xcc->config = config; + + /* Use num_core_regs to see only non-privileged registers in an unmodified + * gdb. Use num_regs to see all registers. gdb modification is required + * for that: reset bit 0 in the 'flags' field of the registers definitions + * in the gdb/xtensa-config.c inside gdb source tree or inside gdb overlay. + */ + cc->gdb_num_core_regs = config->gdb_regmap.num_regs; } void xtensa_register_core(XtensaConfigList *node) |