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| author | Max Filippov <jcmvbkbc@gmail.com> | 2012-09-19 04:23:54 +0400 |
|---|---|---|
| committer | Blue Swirl <blauwirbel@gmail.com> | 2012-09-22 17:59:12 +0000 |
| commit | dd519cbec63434f2b883f0b4a20f827bbd59793e (patch) | |
| tree | 703e0fae97159346ca18b6edfe4c895f7e343570 /target-xtensa/op_helper.c | |
| parent | b81fe822dad134871cd336e26ed55d165e597f4e (diff) | |
| download | qemu-dd519cbec63434f2b883f0b4a20f827bbd59793e.tar.gz | |
target-xtensa: add FP registers
There are 16 32-bit FP registers (f0 - f15), control and status user
registers (fcr, fsr).
See ISA, 4.3.10 for more details.
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
Diffstat (limited to 'target-xtensa/op_helper.c')
| -rw-r--r-- | target-xtensa/op_helper.c | 13 |
1 files changed, 13 insertions, 0 deletions
diff --git a/target-xtensa/op_helper.c b/target-xtensa/op_helper.c index 2659c0e00f..3bf7339511 100644 --- a/target-xtensa/op_helper.c +++ b/target-xtensa/op_helper.c @@ -771,3 +771,16 @@ void HELPER(wsr_dbreakc)(CPUXtensaState *env, uint32_t i, uint32_t v) } env->sregs[DBREAKC + i] = v; } + +void HELPER(wur_fcr)(CPUXtensaState *env, uint32_t v) +{ + static const int rounding_mode[] = { + float_round_nearest_even, + float_round_to_zero, + float_round_up, + float_round_down, + }; + + env->uregs[FCR] = v & 0xfffff07f; + set_float_rounding_mode(rounding_mode[v & 3], &env->fp_status); +} |