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| author | Max Filippov <jcmvbkbc@gmail.com> | 2012-09-19 04:23:56 +0400 |
|---|---|---|
| committer | Blue Swirl <blauwirbel@gmail.com> | 2012-09-22 17:59:12 +0000 |
| commit | 0b6df8385d24a4eed0ff546493c59e047b16537b (patch) | |
| tree | 2be0573070d7cadc07d62bb61b16b92a8d56043f /target-xtensa/translate.c | |
| parent | 9ed7ae12afacdd234a749aa5af27dd93ea1594ec (diff) | |
| download | qemu-0b6df8385d24a4eed0ff546493c59e047b16537b.tar.gz | |
target-xtensa: implement FP0 arithmetic
These are FP arithmetic opcodes.
See ISA, 4.3.10 for more details.
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
Diffstat (limited to 'target-xtensa/translate.c')
| -rw-r--r-- | target-xtensa/translate.c | 61 |
1 files changed, 60 insertions, 1 deletions
diff --git a/target-xtensa/translate.c b/target-xtensa/translate.c index 0f85b36eed..2125b1d00a 100644 --- a/target-xtensa/translate.c +++ b/target-xtensa/translate.c @@ -1907,7 +1907,66 @@ static void disas_xtensa_insn(DisasContext *dc) case 10: /*FP0*/ HAS_OPTION(XTENSA_OPTION_FP_COPROCESSOR); - TBD(); + switch (OP2) { + case 0: /*ADD.Sf*/ + gen_helper_add_s(cpu_FR[RRR_R], cpu_env, + cpu_FR[RRR_S], cpu_FR[RRR_T]); + break; + + case 1: /*SUB.Sf*/ + gen_helper_sub_s(cpu_FR[RRR_R], cpu_env, + cpu_FR[RRR_S], cpu_FR[RRR_T]); + break; + + case 2: /*MUL.Sf*/ + gen_helper_mul_s(cpu_FR[RRR_R], cpu_env, + cpu_FR[RRR_S], cpu_FR[RRR_T]); + break; + + case 4: /*MADD.Sf*/ + gen_helper_madd_s(cpu_FR[RRR_R], cpu_env, + cpu_FR[RRR_R], cpu_FR[RRR_S], cpu_FR[RRR_T]); + break; + + case 5: /*MSUB.Sf*/ + gen_helper_msub_s(cpu_FR[RRR_R], cpu_env, + cpu_FR[RRR_R], cpu_FR[RRR_S], cpu_FR[RRR_T]); + break; + + case 15: /*FP1OP*/ + switch (RRR_T) { + case 0: /*MOV.Sf*/ + tcg_gen_mov_i32(cpu_FR[RRR_R], cpu_FR[RRR_S]); + break; + + case 1: /*ABS.Sf*/ + gen_helper_abs_s(cpu_FR[RRR_R], cpu_FR[RRR_S]); + break; + + case 4: /*RFRf*/ + gen_window_check1(dc, RRR_R); + tcg_gen_mov_i32(cpu_R[RRR_R], cpu_FR[RRR_S]); + break; + + case 5: /*WFRf*/ + gen_window_check1(dc, RRR_S); + tcg_gen_mov_i32(cpu_FR[RRR_R], cpu_R[RRR_S]); + break; + + case 6: /*NEG.Sf*/ + gen_helper_neg_s(cpu_FR[RRR_R], cpu_FR[RRR_S]); + break; + + default: /*reserved*/ + RESERVED(); + break; + } + break; + + default: /*reserved*/ + RESERVED(); + break; + } break; case 11: /*FP1*/ |