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| author | Richard Henderson <rth@twiddle.net> | 2017-02-24 09:12:43 +1100 |
|---|---|---|
| committer | Richard Henderson <rth@twiddle.net> | 2017-02-28 11:41:46 +1100 |
| commit | 5ee4f3c2c750ce55f825116610beb3340daedeca (patch) | |
| tree | f2b2b6ae34634b491cd3b358262418a8fe73fb8e /target/alpha/cpu.h | |
| parent | 8f2d7c341184a95d05476ea3c45dbae2b9ddbe51 (diff) | |
| download | qemu-5ee4f3c2c750ce55f825116610beb3340daedeca.tar.gz | |
target/alpha: Enable MTTCG by default
Alpha has a weak memory ordering and issues all of the required barriers.
Signed-off-by: Richard Henderson <rth@twiddle.net>
Diffstat (limited to 'target/alpha/cpu.h')
| -rw-r--r-- | target/alpha/cpu.h | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/target/alpha/cpu.h b/target/alpha/cpu.h index b08d1601d1..691ac00c0b 100644 --- a/target/alpha/cpu.h +++ b/target/alpha/cpu.h @@ -28,6 +28,9 @@ #define CPUArchState struct CPUAlphaState +/* Alpha processors have a weak memory model */ +#define TCG_GUEST_DEFAULT_MO (0) + #include "exec/cpu-defs.h" #include "fpu/softfloat.h" |