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| author | Peter Maydell <peter.maydell@linaro.org> | 2017-07-31 14:45:42 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2017-07-31 14:45:42 +0100 |
| commit | 5619c179057e24195ff19c8fe6d6a6cbcb16ed28 (patch) | |
| tree | 5d2f1166996202e5d26cc5a59098ec8ef0634b7f /target/arm/cpu.h | |
| parent | bdf211f884113426e1f8226b69731593efa003ea (diff) | |
| parent | 89cbc3778a3d61761e2231e740269218c9a8a41d (diff) | |
| download | qemu-5619c179057e24195ff19c8fe6d6a6cbcb16ed28.tar.gz | |
Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20170731' into staging
target-arm queue:
* fix broken properties on MPS2 SCC device
* fix MPU trace handling of write vs exec
* fix MPU M profile bugs:
- not handling system space or PPB region correctly
- not resetting state
- not migrating MPU_RNR
# gpg: Signature made Mon 31 Jul 2017 13:21:40 BST
# gpg: using RSA key 0x3C2525ED14360CDE
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>"
# gpg: aka "Peter Maydell <pmaydell@gmail.com>"
# gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>"
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE
* remotes/pmaydell/tags/pull-target-arm-20170731:
hw/mps2_scc: fix incorrect properties
target/arm: Migrate MPU_RNR register state for M profile cores
target/arm: Move PMSAv7 reset into arm_cpu_reset() so M profile MPUs get reset
target/arm: Rename cp15.c6_rgnr to pmsav7.rnr
target/arm: Don't allow guest to make System space executable for M profile
target/arm: Don't do MPU lookups for addresses in M profile PPB region
target/arm: Correct MPU trace handling of write vs execute
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target/arm/cpu.h')
| -rw-r--r-- | target/arm/cpu.h | 3 |
1 files changed, 1 insertions, 2 deletions
diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 102c58afac..b39d64aa0b 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -305,8 +305,6 @@ typedef struct CPUARMState { uint64_t par_el[4]; }; - uint32_t c6_rgnr; - uint32_t c9_insn; /* Cache lockdown registers. */ uint32_t c9_data; uint64_t c9_pmcr; /* performance monitor control register */ @@ -519,6 +517,7 @@ typedef struct CPUARMState { uint32_t *drbar; uint32_t *drsr; uint32_t *dracr; + uint32_t rnr; } pmsav7; void *nvic; |