diff options
| author | James Hogan <james.hogan@imgtec.com> | 2017-07-31 14:09:13 +0100 |
|---|---|---|
| committer | Yongbok Kim <yongbok.kim@imgtec.com> | 2017-08-02 22:18:06 +0100 |
| commit | d3d93c6c1eb0d94d2f203ac272629e6ebfc468a7 (patch) | |
| tree | 83d3af6e6b6e4805be622337ebf354b3681b95a5 /target/mips/translate.c | |
| parent | 6743334568933199927af4992a04bfb3c30610f5 (diff) | |
| download | qemu-d3d93c6c1eb0d94d2f203ac272629e6ebfc468a7.tar.gz | |
mips: Add KVM T&E segment support for TCG
MIPS KVM trap & emulate guest kernels have a different segment layout
compared with traditional MIPS kernels, to allow both the user and
kernel code to run from the user address segment without repeatedly
trapping to KVM.
QEMU currently supports this layout only for KVM, but its sometimes
useful to be able to run these kernels in QEMU on a PC, so enable it for
TCG too.
This also paves the way for MIPS KVM VZ support (which uses the normal
virtual memory layout) by abstracting whether user mode kernel segments
are in use.
Suggested-by: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: James Hogan <james.hogan@imgtec.com>
Cc: Yongbok Kim <yongbok.kim@imgtec.com>
Cc: Aurelien Jarno <aurelien@aurel32.net>
Cc: Paolo Bonzini <pbonzini@redhat.com>
Cc: kvm@vger.kernel.org
Reviewed-by: Richard Henderson <rth@twiddle.net>
[Yongbok Kim:
minor change]
Signed-off-by: Yongbok Kim <yongbok.kim@imgtec.com>
Diffstat (limited to 'target/mips/translate.c')
| -rw-r--r-- | target/mips/translate.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/target/mips/translate.c b/target/mips/translate.c index 0bca700fb3..88f518b43c 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -27,10 +27,10 @@ #include "exec/exec-all.h" #include "tcg-op.h" #include "exec/cpu_ldst.h" +#include "hw/mips/cpudevs.h" #include "exec/helper-proto.h" #include "exec/helper-gen.h" -#include "sysemu/kvm.h" #include "exec/semihost.h" #include "target/mips/trace.h" @@ -20635,7 +20635,7 @@ void cpu_state_reset(CPUMIPSState *env) env->CP0_Wired = 0; env->CP0_GlobalNumber = (cs->cpu_index & 0xFF) << CP0GN_VPId; env->CP0_EBase = (cs->cpu_index & 0x3FF); - if (kvm_enabled()) { + if (mips_um_ksegs_enabled()) { env->CP0_EBase |= 0x40000000; } else { env->CP0_EBase |= (int32_t)0x80000000; |