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| author | Stafford Horne <shorne@gmail.com> | 2017-04-06 06:44:56 +0900 |
|---|---|---|
| committer | Stafford Horne <shorne@gmail.com> | 2017-05-04 09:39:01 +0900 |
| commit | d89e71e873dca0ca6d3b3adab283045a03f4ca99 (patch) | |
| tree | 1aa8a808dd445d9f57a65affc72a3b03d3e93cbe /target/openrisc/translate.c | |
| parent | 4597992f624c015ceb51fedb4628b3fdb1e5bbaa (diff) | |
| download | qemu-d89e71e873dca0ca6d3b3adab283045a03f4ca99.tar.gz | |
target/openrisc: implement shadow registers
Shadow registers are part of the openrisc spec along with sr[cid], as
part of the fast context switching feature. When exceptions occur,
instead of having to save registers to the stack if enabled the CID will
increment and a new set of registers will be available.
This patch only implements shadow registers which can be used as extra
scratch registers via the mfspr and mtspr if required. This is
implemented in a way where it would be easy to add on the fast context
switching, currently cid is hardcoded to 0.
This is need for openrisc linux smp kernels to boot correctly.
Signed-off-by: Stafford Horne <shorne@gmail.com>
Diffstat (limited to 'target/openrisc/translate.c')
| -rw-r--r-- | target/openrisc/translate.c | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/target/openrisc/translate.c b/target/openrisc/translate.c index 7c4cbf205f..e49518e893 100644 --- a/target/openrisc/translate.c +++ b/target/openrisc/translate.c @@ -107,7 +107,8 @@ void openrisc_translate_init(void) "mac"); for (i = 0; i < 32; i++) { cpu_R[i] = tcg_global_mem_new(cpu_env, - offsetof(CPUOpenRISCState, gpr[i]), + offsetof(CPUOpenRISCState, + shadow_gpr[0][i]), regnames[i]); } cpu_R0 = cpu_R[0]; @@ -1662,7 +1663,7 @@ void openrisc_cpu_dump_state(CPUState *cs, FILE *f, cpu_fprintf(f, "PC=%08x\n", env->pc); for (i = 0; i < 32; ++i) { - cpu_fprintf(f, "R%02d=%08x%c", i, env->gpr[i], + cpu_fprintf(f, "R%02d=%08x%c", i, cpu_get_gpr(env, i), (i % 4) == 3 ? '\n' : ' '); } } |