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authorEdgar E. Iglesias <edgar.iglesias@xilinx.com>2018-04-15 23:21:06 +0200
committerEdgar E. Iglesias <edgar.iglesias@xilinx.com>2018-04-30 16:43:20 +0200
commitfce6a8eceb07e27f0cdea87427f4e560dfa0b1c8 (patch)
tree44535e4976833788e9c3ff191fcac5461062d506 /target
parentbd9e66086b93a0a908a70a2679819d2d080d87b4 (diff)
downloadqemu-fce6a8eceb07e27f0cdea87427f4e560dfa0b1c8.tar.gz
target-microblaze: mmu: Make the TLBX MISS bit read-only
Make the TLBX MISS bit read-only. Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Diffstat (limited to 'target')
-rw-r--r--target/microblaze/mmu.c4
1 files changed, 4 insertions, 0 deletions
diff --git a/target/microblaze/mmu.c b/target/microblaze/mmu.c
index 8391811900..9d5e6aa8a5 100644
--- a/target/microblaze/mmu.c
+++ b/target/microblaze/mmu.c
@@ -273,6 +273,10 @@ void mmu_write(CPUMBState *env, uint32_t rn, uint32_t v)
env->mmu.regs[rn] = v;
}
break;
+ case MMU_R_TLBX:
+ /* Bit 31 is read-only. */
+ env->mmu.regs[rn] = deposit32(env->mmu.regs[rn], 0, 31, v);
+ break;
case MMU_R_TLBSX:
{
struct microblaze_mmu_lookup lu;