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| author | Peter Maydell <peter.maydell@linaro.org> | 2017-03-06 13:06:30 +0000 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2017-03-06 13:06:30 +0000 |
| commit | 56b51708e9e22809d2a78f38d0ac84bb3f3fca92 (patch) | |
| tree | 408143cc245930ae0a59bec0a88418f14b79e6d3 /target | |
| parent | fbddc2e5608eb655493253d080598375db61a748 (diff) | |
| parent | 182fe2cf19e829e34f63443ee1ccd9f799715c2c (diff) | |
| download | qemu-56b51708e9e22809d2a78f38d0ac84bb3f3fca92.tar.gz | |
Merge remote-tracking branch 'remotes/dgibson/tags/ppc-for-2.9-20170306' into staging
ppc patch queue for 2017-03-06
Looks like my previous batch wasn't quite the last before hard freeze.
This has a handful of bugfixes to go in. They're all genuine
bugfixes, though not regressions in some cases.
# gpg: Signature made Mon 06 Mar 2017 04:07:48 GMT
# gpg: using RSA key 0x6C38CACA20D9B392
# gpg: Good signature from "David Gibson <david@gibson.dropbear.id.au>"
# gpg: aka "David Gibson (Red Hat) <dgibson@redhat.com>"
# gpg: aka "David Gibson (ozlabs.org) <dgibson@ozlabs.org>"
# gpg: aka "David Gibson (kernel.org) <dwg@kernel.org>"
# Primary key fingerprint: 75F4 6586 AE61 A66C C44E 87DC 6C38 CACA 20D9 B392
* remotes/dgibson/tags/ppc-for-2.9-20170306:
target/ppc: use helper for excp handling
target/ppc: fmadd: add macro for updating flags
target/ppc: fmadd check for excp independently
spapr: ensure that all threads within core are on the same NUMA node
ppc/xics: register reset handlers for the ICP and ICS objects
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target')
| -rw-r--r-- | target/ppc/fpu_helper.c | 77 |
1 files changed, 32 insertions, 45 deletions
diff --git a/target/ppc/fpu_helper.c b/target/ppc/fpu_helper.c index 0535ad0814..c4dab159e4 100644 --- a/target/ppc/fpu_helper.c +++ b/target/ppc/fpu_helper.c @@ -743,34 +743,38 @@ uint64_t helper_frim(CPUPPCState *env, uint64_t arg) return do_fri(env, arg, float_round_down); } -static void float64_maddsub_update_excp(CPUPPCState *env, float64 arg1, - float64 arg2, float64 arg3, - unsigned int madd_flags) -{ - if (unlikely((float64_is_infinity(arg1) && float64_is_zero(arg2)) || - (float64_is_zero(arg1) && float64_is_infinity(arg2)))) { - /* Multiplication of zero by infinity */ - arg1 = float_invalid_op_excp(env, POWERPC_EXCP_FP_VXIMZ, 1); - } else if (unlikely(float64_is_signaling_nan(arg1, &env->fp_status) || - float64_is_signaling_nan(arg2, &env->fp_status) || - float64_is_signaling_nan(arg3, &env->fp_status))) { - /* sNaN operation */ - float_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 1); - } else if ((float64_is_infinity(arg1) || float64_is_infinity(arg2)) && - float64_is_infinity(arg3)) { - uint8_t aSign, bSign, cSign; - - aSign = float64_is_neg(arg1); - bSign = float64_is_neg(arg2); - cSign = float64_is_neg(arg3); - if (madd_flags & float_muladd_negate_c) { - cSign ^= 1; - } - if (aSign ^ bSign ^ cSign) { - float_invalid_op_excp(env, POWERPC_EXCP_FP_VXISI, 1); - } - } +#define FPU_MADDSUB_UPDATE(NAME, TP) \ +static void NAME(CPUPPCState *env, TP arg1, TP arg2, TP arg3, \ + unsigned int madd_flags) \ +{ \ + if (TP##_is_signaling_nan(arg1, &env->fp_status) || \ + TP##_is_signaling_nan(arg2, &env->fp_status) || \ + TP##_is_signaling_nan(arg3, &env->fp_status)) { \ + /* sNaN operation */ \ + float_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 1); \ + } \ + if ((TP##_is_infinity(arg1) && TP##_is_zero(arg2)) || \ + (TP##_is_zero(arg1) && TP##_is_infinity(arg2))) { \ + /* Multiplication of zero by infinity */ \ + float_invalid_op_excp(env, POWERPC_EXCP_FP_VXIMZ, 1); \ + } \ + if ((TP##_is_infinity(arg1) || TP##_is_infinity(arg2)) && \ + TP##_is_infinity(arg3)) { \ + uint8_t aSign, bSign, cSign; \ + \ + aSign = TP##_is_neg(arg1); \ + bSign = TP##_is_neg(arg2); \ + cSign = TP##_is_neg(arg3); \ + if (madd_flags & float_muladd_negate_c) { \ + cSign ^= 1; \ + } \ + if (aSign ^ bSign ^ cSign) { \ + float_invalid_op_excp(env, POWERPC_EXCP_FP_VXISI, 1); \ + } \ + } \ } +FPU_MADDSUB_UPDATE(float32_maddsub_update_excp, float32) +FPU_MADDSUB_UPDATE(float64_maddsub_update_excp, float64) #define FPU_FMADD(op, madd_flags) \ uint64_t helper_##op(CPUPPCState *env, uint64_t arg1, \ @@ -2236,24 +2240,7 @@ void helper_##op(CPUPPCState *env, uint32_t opcode) \ env->fp_status.float_exception_flags |= tstat.float_exception_flags; \ \ if (unlikely(tstat.float_exception_flags & float_flag_invalid)) { \ - if (tp##_is_signaling_nan(xa.fld, &tstat) || \ - tp##_is_signaling_nan(b->fld, &tstat) || \ - tp##_is_signaling_nan(c->fld, &tstat)) { \ - float_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, sfprf); \ - tstat.float_exception_flags &= ~float_flag_invalid; \ - } \ - if ((tp##_is_infinity(xa.fld) && tp##_is_zero(b->fld)) || \ - (tp##_is_zero(xa.fld) && tp##_is_infinity(b->fld))) { \ - xt_out.fld = float64_to_##tp(float_invalid_op_excp(env, \ - POWERPC_EXCP_FP_VXIMZ, sfprf), &env->fp_status); \ - tstat.float_exception_flags &= ~float_flag_invalid; \ - } \ - if ((tstat.float_exception_flags & float_flag_invalid) && \ - ((tp##_is_infinity(xa.fld) || \ - tp##_is_infinity(b->fld)) && \ - tp##_is_infinity(c->fld))) { \ - float_invalid_op_excp(env, POWERPC_EXCP_FP_VXISI, sfprf); \ - } \ + tp##_maddsub_update_excp(env, xa.fld, b->fld, c->fld, maddflgs); \ } \ \ if (r2sp) { \ |