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| author | Richard Henderson <rth@twiddle.net> | 2014-03-26 10:59:14 -0700 |
|---|---|---|
| committer | Richard Henderson <rth@twiddle.net> | 2014-04-18 16:57:37 -0700 |
| commit | df9ebea53ebc1c98217743f56c30ae3a46031bb9 (patch) | |
| tree | c0ca7191f6e26e1975e36ac180699742f3ae31d2 /tcg/mips | |
| parent | 671c835b7dc12bfb3907c6af38f74073fe8fade9 (diff) | |
| download | qemu-df9ebea53ebc1c98217743f56c30ae3a46031bb9.tar.gz | |
tcg: Relax requirement for mulu2_i32 on 32-bit hosts
Instead require either mulu2_i32 or muluh_i32. The code in tcg-op.h
already supports looking for both. Previous incomplete conversion?
Signed-off-by: Richard Henderson <rth@twiddle.net>
Diffstat (limited to 'tcg/mips')
| -rw-r--r-- | tcg/mips/tcg-target.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/tcg/mips/tcg-target.h b/tcg/mips/tcg-target.h index 683c6af8b9..c3822d0d4c 100644 --- a/tcg/mips/tcg-target.h +++ b/tcg/mips/tcg-target.h @@ -109,6 +109,7 @@ extern bool use_mips32r2_instructions; #define TCG_TARGET_HAS_orc_i32 0 #define TCG_TARGET_HAS_eqv_i32 0 #define TCG_TARGET_HAS_nand_i32 0 +#define TCG_TARGET_HAS_mulu2_i32 1 #define TCG_TARGET_HAS_muls2_i32 1 #define TCG_TARGET_HAS_muluh_i32 1 #define TCG_TARGET_HAS_mulsh_i32 1 |