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authorAurelien Jarno <aurelien@aurel32.net>2010-03-27 16:32:55 +0100
committerAurelien Jarno <aurelien@aurel32.net>2010-03-27 16:32:55 +0100
commit2b79487a56d58f65d14f7040e118da9f7724f4a2 (patch)
tree1225de6cdfa95f1450908a61be8c66969b1645be /tcg/mips
parent6adc05492fce75b530b3534cb6ec055ac3b4afb5 (diff)
downloadqemu-2b79487a56d58f65d14f7040e118da9f7724f4a2.tar.gz
tcg-mips: implement nor
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Diffstat (limited to 'tcg/mips')
-rw-r--r--tcg/mips/tcg-target.c4
-rw-r--r--tcg/mips/tcg-target.h2
2 files changed, 5 insertions, 1 deletions
diff --git a/tcg/mips/tcg-target.c b/tcg/mips/tcg-target.c
index f7ed0baedd..a0c5289df0 100644
--- a/tcg/mips/tcg-target.c
+++ b/tcg/mips/tcg-target.c
@@ -1239,6 +1239,9 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc,
tcg_out_opc_reg(s, OPC_OR, args[0], args[1], args[2]);
}
break;
+ case INDEX_op_nor_i32:
+ tcg_out_opc_reg(s, OPC_NOR, args[0], args[1], args[2]);
+ break;
case INDEX_op_not_i32:
tcg_out_opc_reg(s, OPC_NOR, args[0], args[1], args[1]);
break;
@@ -1350,6 +1353,7 @@ static const TCGTargetOpDef mips_op_defs[] = {
{ INDEX_op_sub_i32, { "r", "rZ", "rJZ" } },
{ INDEX_op_and_i32, { "r", "rZ", "rIZ" } },
+ { INDEX_op_nor_i32, { "r", "rZ", "rZ" } },
{ INDEX_op_not_i32, { "r", "rZ" } },
{ INDEX_op_or_i32, { "r", "rZ", "rIZ" } },
{ INDEX_op_xor_i32, { "r", "rZ", "rIZ" } },
diff --git a/tcg/mips/tcg-target.h b/tcg/mips/tcg-target.h
index 63d7f9a500..5f8b00a9b8 100644
--- a/tcg/mips/tcg-target.h
+++ b/tcg/mips/tcg-target.h
@@ -80,6 +80,7 @@ enum {
/* optional instructions */
#define TCG_TARGET_HAS_div_i32
#define TCG_TARGET_HAS_not_i32
+#define TCG_TARGET_HAS_nor_i32
#undef TCG_TARGET_HAS_rot_i32
#undef TCG_TARGET_HAS_ext8s_i32
#undef TCG_TARGET_HAS_ext16s_i32
@@ -89,7 +90,6 @@ enum {
#undef TCG_TARGET_HAS_orc_i32
#undef TCG_TARGET_HAS_eqv_i32
#undef TCG_TARGET_HAS_nand_i32
-#undef TCG_TARGET_HAS_nor_i32
/* optional instructions automatically implemented */
#undef TCG_TARGET_HAS_neg_i32 /* sub rd, zero, rt */