diff options
| author | Richard Henderson <rth@twiddle.net> | 2015-05-12 11:51:44 -0700 |
|---|---|---|
| committer | Richard Henderson <rth@twiddle.net> | 2015-05-14 12:14:55 -0700 |
| commit | 59227d5d45bb3c31dc2118011691c35b3c00879c (patch) | |
| tree | bb7a884bf0fb334f9ab104c7051aca91d9e0e79a /tcg/tcg-op.c | |
| parent | 1eeace9c237a729d11c7acd7c0338ab4562af637 (diff) | |
| download | qemu-59227d5d45bb3c31dc2118011691c35b3c00879c.tar.gz | |
tcg: Merge memop and mmu_idx parameters to qemu_ld/st
At the tcg opcode level, not at the tcg-op.h generator level.
This requires minor changes through all of the tcg backends,
but none of the cpu translators.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <rth@twiddle.net>
Diffstat (limited to 'tcg/tcg-op.c')
| -rw-r--r-- | tcg/tcg-op.c | 22 |
1 files changed, 10 insertions, 12 deletions
diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c index 2b6be756ba..45098c310e 100644 --- a/tcg/tcg-op.c +++ b/tcg/tcg-op.c @@ -1873,15 +1873,14 @@ static inline TCGMemOp tcg_canonicalize_memop(TCGMemOp op, bool is64, bool st) static void gen_ldst_i32(TCGOpcode opc, TCGv_i32 val, TCGv addr, TCGMemOp memop, TCGArg idx) { + TCGMemOpIdx oi = make_memop_idx(memop, idx); #if TARGET_LONG_BITS == 32 - tcg_gen_op4ii_i32(opc, val, addr, memop, idx); + tcg_gen_op3i_i32(opc, val, addr, oi); #else if (TCG_TARGET_REG_BITS == 32) { - tcg_gen_op5ii_i32(opc, val, TCGV_LOW(addr), TCGV_HIGH(addr), - memop, idx); + tcg_gen_op4i_i32(opc, val, TCGV_LOW(addr), TCGV_HIGH(addr), oi); } else { - tcg_gen_op4(&tcg_ctx, opc, GET_TCGV_I32(val), GET_TCGV_I64(addr), - memop, idx); + tcg_gen_op3(&tcg_ctx, opc, GET_TCGV_I32(val), GET_TCGV_I64(addr), oi); } #endif } @@ -1889,20 +1888,19 @@ static void gen_ldst_i32(TCGOpcode opc, TCGv_i32 val, TCGv addr, static void gen_ldst_i64(TCGOpcode opc, TCGv_i64 val, TCGv addr, TCGMemOp memop, TCGArg idx) { + TCGMemOpIdx oi = make_memop_idx(memop, idx); #if TARGET_LONG_BITS == 32 if (TCG_TARGET_REG_BITS == 32) { - tcg_gen_op5ii_i32(opc, TCGV_LOW(val), TCGV_HIGH(val), - addr, memop, idx); + tcg_gen_op4i_i32(opc, TCGV_LOW(val), TCGV_HIGH(val), addr, oi); } else { - tcg_gen_op4(&tcg_ctx, opc, GET_TCGV_I64(val), GET_TCGV_I32(addr), - memop, idx); + tcg_gen_op3(&tcg_ctx, opc, GET_TCGV_I64(val), GET_TCGV_I32(addr), oi); } #else if (TCG_TARGET_REG_BITS == 32) { - tcg_gen_op6ii_i32(opc, TCGV_LOW(val), TCGV_HIGH(val), - TCGV_LOW(addr), TCGV_HIGH(addr), memop, idx); + tcg_gen_op5i_i32(opc, TCGV_LOW(val), TCGV_HIGH(val), + TCGV_LOW(addr), TCGV_HIGH(addr), oi); } else { - tcg_gen_op4ii_i64(opc, val, addr, memop, idx); + tcg_gen_op3i_i64(opc, val, addr, oi); } #endif } |